Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
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Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/9bf1e9f6_5095c656
PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Let's wait Subrata for update.
Looks like in order to use x1 DT slot (RP8) at PCH side, we need to make sure CLKSRC -> 7 and CLKREQ -> 6. As CLKREQ 6 is used for both PCH LAN and RP8 hence we need to make it as free running clock rather assign to particular RP as other PCIe CLK does
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