Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3822
-gerrit
commit 19b34834e36456bcc652e0da881e26ddc8c5eeb8 Author: Mike Loptien mike.loptien@se-eng.com Date: Thu Jul 18 10:16:31 2013 -0600
AMD Fam16: Add secondary bus number to CRES method
Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the AMD FCH ACPI code. This sets up the bus number for the PCI0 device and the secondary bus number in the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. PCI busses can have up to 256 secondary busses connected to them via a PCI-PCI bridge. However, these busses do not have to be sequentially numbered, so leaving out a section of the range (eg. allowing [0-0x7F]) will unnecessarily restrict the downstream busses.
This is the same change that was made on Family14 in this patch: 26855fc: AMD Fam14 DSDT: Add secondary bus range to PCI0
Change-Id: Ib2d36f69a26b715798ef1ea17deb0905fa0cad87 Signed-off-by: Mike Loptien mike.loptien@se-eng.com Reviewed-by: Marc Jones marc.jones@se-eng.com Tested-by: Bruce Griffith bruce.griffith@se-eng.com --- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 4fbf853..5d3a29c 100755 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -71,6 +71,22 @@ Device(ACMD) { #endif
Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,