build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39167 )
Change subject: soc/tigerlake: Correct FSP log interface
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39167/1/src/soc/intel/tigerlake/rom...
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39167/1/src/soc/intel/tigerlake/rom...
PS1, Line 64: DEBUG_INTERFACE_UART|DEBUG_INTERFACE_TRACEHUB : \
Avoid unnecessary line continuations
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67
Gerrit-Change-Number: 39167
Gerrit-PatchSet: 1
Gerrit-Owner: Wonkyu Kim
wonkyu.kim@intel.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Wonkyu Kim
wonkyu.kim@intel.com
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Gerrit-Comment-Date: Sat, 29 Feb 2020 01:22:42 +0000
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