[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Skip CSE post hook when CSE is disabled

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58513 )

Change subject: soc/intel/common: Skip CSE post hook when CSE is disabled
......................................................................

soc/intel/common: Skip CSE post hook when CSE is disabled

This patch fixes regression introduced by commit bee4bb5f0
(soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM)
FAFT test case fail when doing `firmware_DevMode` test.

If CSE is already hidden then accessing CSE registers would be wrong
and will receive junk, hence, return as CSE is already disabled.

BUG=b:203061531
TEST=Brya system can boot to OS with recovery mode.

Change-Id: I2046eb19716c397a066c2c41e1b027a256bd6cf9
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58513
Tested-by: build bot (Jenkins) 
Reviewed-by: Rizwan Qureshi 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/common/block/cse/cse_eop.c
1 file changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Rizwan Qureshi: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c
index 1f54469..e47eb51 100644
--- a/src/soc/intel/common/block/cse/cse_eop.c
+++ b/src/soc/intel/common/block/cse/cse_eop.c
@@ -175,6 +175,15 @@

static void set_cse_end_of_post(void *unused)
 {
+	/*
+	 * If CSE is already hidden then accessing CSE registers would be wrong and will
+	 * receive junk, hence, return as CSE is already disabled.
+	 */
+	if (!is_cse_enabled()) {
+		printk(BIOS_DEBUG, "CSE is disabled, cannot send End-of-Post (EOP) message\n");
+		return;
+	}
+
    set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE);

timestamp_add_now(TS_ME_BEFORE_END_OF_POST);