Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41375 )
Change subject: nb/intel/sandybridge: Do not hardcode resource indices ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41375/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/northbridge.c:
https://review.coreboot.org/c/coreboot/+/41375/1/src/northbridge/intel/sandy... PS1, Line 138: 3
I checked, and this had been hardcoded since forever (ever since sandybridge was added) […]
Hmmm, maybe just keep it in mind. Some infrastructure to allocate the index for random resources would be nice. I've looked at many northbridges, and all I can tell is that some hardcoded 10, some hardcoded 3.
For not so random resources, the index is determined by the BAR reg's offset. So we have an upper limit for PCI, where the registers start at 16. But I can't find no clue why we don't start at 0.