[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: add option for SLP_S3_L assertion width

the following patch was just integrated into master:
commit 41a3fa66a0d8a6b134ceb17b8f34520cad7643a4
Author: Aaron Durbin 
Date:   Thu Aug 25 15:42:04 2016 -0500

soc/intel/apollolake: add option for SLP_S3_L assertion width

In order to provide time for the S0 rails to discharge one needs
    to be able to set the SLP_S3_L assertion width. The hardware default
    is 60 microcseconds which is not slow enough on most boards. Therefore
    provide a devicetree option for the mainboard to set accordingly
    for its needs. An unset value in devicetree results in a conservative
    2 second SLP_S3_L duration.

BUG=chrome-os-partner:56581

Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50
    Signed-off-by: Aaron Durbin 
    Reviewed-on: https://review.coreboot.org/16326
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel 
    Reviewed-by: Andrey Petrov

See https://review.coreboot.org/16326 for details.

-gerrit