[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer: Add boldar GPIO configuration

7 Oct 2020

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46131 )
Change subject: mb/google/volteer: Add boldar GPIO configuration
......................................................................
mb/google/volteer: Add boldar GPIO configuration
Change-Id: I214a615e8104c181c96c88dae6bd9278ed6250ab
Signed-off-by: Aamir Bohra aamir.bohra@intel.com
---
A src/mainboard/google/volteer/variants/boldar/Makefile.inc
A src/mainboard/google/volteer/variants/boldar/gpio.c
2 files changed, 301 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46131/1

diff --git a/src/mainboard/google/volteer/variants/boldar/Makefile.inc b/src/mainboard/google/volteer/variants/boldar/Makefile.inc
new file mode 100644
index 0000000..13269db
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/boldar/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/boldar/gpio.c b/src/mainboard/google/volteer/variants/boldar/gpio.c
new file mode 100644
index 0000000..f429adf
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/boldar/gpio.c
@@ -0,0 +1,296 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+
+	/* A5 : USB_C0_AUXP_DC */
+	PAD_CFG_GPO(GPP_A5, 1, DEEP),
+	/* A6 : USB_C0_AUXN_DC */
+	PAD_CFG_GPO(GPP_A6, 1, DEEP),
+	/* A8 : EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_A8, NONE, DEEP),
+	/* A9 : ESPI_CLK */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+	/* A10 : ESPI_RST_L */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+	/* A13 : BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
+	/* A16 : USB_C0_OC_ODL */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A18 : HDMI_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A21 : EN_FP_PWR */
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
+	/* A22 : EN_HDMI_PWR */
+	PAD_CFG_GPO(GPP_A22, 1, DEEP),
+	/* A23 : EN_SPKR_PA */
+	PAD_CFG_GPO(GPP_A23, 1, DEEP),
+
+	/* B3 : PEN_DET_ODL */
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+	/* B4 : WiFi_DISABLE_L */
+	PAD_CFG_GPO(GPP_B4, 0, DEEP),
+	/* B5 : ISH_I2C0_CVF_SDA */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	/* B6 : ISH_I2C0_CVF_SCL */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+	/* B7 : ISH_I2C0_SENSOR_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8 : ISH_I2C0_SENSOR_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/* B9 : NC */
+	PAD_NC(GPP_B9, UP_20K),
+	/* B10 : NC */
+	PAD_NC(GPP_B10, UP_20K),
+	/* B15 : FPMCU_INT_L */
+	PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, LEVEL),
+	/* B16 : PCH_I2C5_TRACKPAD_SDA */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+	/* B17 : PCH_I2C5_TRACKPAD_SCL */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+	/* B18 : EN_PP5000_TRACKPAD */
+	PAD_CFG_GPO(GPP_B18, 1, DEEP),
+	/* B19 : NC */
+	PAD_NC(GPP_B19, UP_20K),
+	/* B20 : NC */
+	PAD_NC(GPP_B20, UP_20K),
+	/* B21 : NC */
+	PAD_NC(GPP_B21, UP_20K),
+	/* B22 : NC */
+	PAD_NC(GPP_B22, UP_20K),
+
+	/* C0 : EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1 : USI_RST_L */
+	PAD_CFG_GPO(GPP_C1, 0, DEEP),
+	/* C3 : H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT)
+	/* C4 : EN_PP5000_PEN */
+	PAD_CFG_GPO(GPP_C4, 1, DEEP),
+	/* C7 : FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C7, 1, DEEP),
+
+	/* D0 : SSD_RTD3_EN */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP),
+	/* D1 : ISH_ACCEL_INT_L */
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+	/* D2 : ISH_LID_OPEN */
+	PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+	/* D3 : ISH_ALS_RGB_INT_L */
+	PAD_CFG_GPI(GPP_D3, NONE, DEEP),
+	/* D4 : FCAM_RST_L */
+	PAD_CFG_GPO(GPP_D4, 0, PLTRST),
+	/* D6 : WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* D8 : SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D9 : SD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+	/* D10 : EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_D10, 1, DEEP),
+	/* D11 : PEN_ALERT_ODL */
+	PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+	/* D12 : PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_D12, 0, DEEP)
+	/* D13 : UART_ISH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : UART_ISH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D16 : EN_PP3300_SD */
+	PAD_NC(GPP_D16, UP_20K),
+	/* D17 : EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
+	/* D18 : FCAM_SNRPWR_EN */
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+
+	/* E1 : PEN_DET_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+	/* E2 : WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	/* E3 : USI_REPORT_EN */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),
+	/* E7 : USI_INT */
+	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+	/* E8 : SLP_S0IX */
+	PAD_CFG_GPO(GPP_E8, 0, DEEP),
+
+	/* E10 : PCH_GSPI0_H1_TPM_CS_L */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	/* E11 : PCH_GSPI0_H1_TPM_CLK */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	/* E12 : PCH_GSPIO_H1_TPM_MISO */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+	/* E15 : TRACKPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+	/* E16 : WWAN_SIM1_DET_OD */
+	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
+	/* E17 : WWAN_PERST_L */
+	PAD_CFG_GPO(GPP_E17, 1, DEEP),
+
+	/* F6  : WWAN_CONFIG3 */
+	PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+	/* A7  : EN_PP3300_TRACKPAD */
+	PAD_CFG_GPO(GPP_F7, 1, DEEP),
+	/* F9  : HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, EDGE_BOTH),
+	/* F10 : EN_PP3300_TOUCHSCREEN */
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	/* F11 : PCH_GSPI1_FPMCU_CLK */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+	/* F12 : PCH_GSPI1_FPMCU_MISO */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+	/* F13 : PCH_GSPI1_FPMCU_MISO */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F14 : WLAN_RST_ODL */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F15 : RCAM_RST_L */
+	PAD_CFG_GPO(GPP_F15, 1, DEEP),
+	/* F16 : PCH_GSPI1_FPMCU_CS_L */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+	/* F17 : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_F17, 1, DEEP),
+	/* F18 : WWAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
+	/* F19 : WLAN_INT_L */
+	PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+	/* F20 : WWAN_RST_ODL */
+	PAD_CFG_GPI(GPP_F20, NONE, DEEP),
+	/* F21 : WWAN_DPR_SAR_ODL */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+
+	/* H3 : SD_PERST_L */
+	PAD_CFG_GPO(GPP_H3, 1, DEEP),
+	/* H4 : PCH_I2C0_MISC_SCL */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5 : PCH_I2C0_MISC_SDA */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H6 : PCH_I2C1_CAM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7 : PCH_I2C1_CAM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8 : WWAN_WLAN_COEX1 */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+	/* H9 : WWAN_WLAN_COEX2 */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+	/* H10 : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+	/* H11 : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+	/* H12 : WWAN_CONFIG0 */
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+	/* H14 : RCAM_SNRPWR_EN */
+	PAD_CFG_GPO(GPP_H13, 0, DEEP),
+	/* H15 : DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H17 : DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H19 : USB_C1_RT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_H19, 1, DEEP),
+	/* H20 : EN_MIPI_RCAM_PWR */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* H21 : CAM_MCLK1 */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* H22 : CAM_MCLK0 */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+	/* R0 : I2S0_HP_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* R1 : I2S0_HP_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* R2 : I2S0_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+	/* R3 : I2S0_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+	/* R4 : DMIC_CLK0 */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+	/* R5 : DMIC_DATA0 */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+	/* R6 : WWAN_WLAN_COEX3 */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
+	/* R7 : SAR0_INT_L */
+	PAD_CFG_GPI_APIC(GPP_R7, NONE, PLTRST, LEVEL, NONE),
+
+	/* S0 : I2S1_SPKR_SCLK */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2),
+	/* S1 : I2S1_SPKR_SFRM */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2),
+	/* S2 : I2S1_PCH_TX_SPKR_RX */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3),
+	/* S3 : I2S1_PCH_TX_SPKR_RX */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3),
+	/* S5 : SPKR_INT_L */
+	PAD_CFG_GPI_APIC(GPP_S5, NONE, PLTRST, LEVEL, NONE),
+	/* S6 : DMIC_CLK1 */
+	PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
+	/* S7 : DMIC_DATA1 */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* GPD9: SLP_WLAN_L */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+	/* A7 : MEM_STRAP_0 */
+	PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+	/* A12 : M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* A17 : MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+	/* A19 : MEM_STRAP_2 */
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+	/* A20 : MEM_STRAP_1 */
+	PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+
+	/* B11 : PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+
+	/* C0 : EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1 : H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C1, NONE, PLTRST, LEVEL, INVERT),
+
+	/* D10 : EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_D10, 1, DEEP),
+	/* D12 : PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),
+	/* D15 : MEM_STRAP_3 */
+	PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+	/* D16 : EN_PP3300_SD */
+	PAD_NC(GPP_D16, UP_20K),
+
+	/* E10 : PCH_GSPI0_H1_TPM_CS_L */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+	/* E11 : PCH_GSPI0_H1_TPM_CLK */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+	/* E12 : PCH_GSPIO_H1_TPM_MISO */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+	/* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+
+	/* F14 : WLAN_PERST_L */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F20 : WWAN_RST_ODL
+	   To meet timing constrains - drive reset low.
+	   Deasserted in ramstage. */
+	PAD_CFG_GPO(GPP_F20, 0, DEEP),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/46131
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I214a615e8104c181c96c88dae6bd9278ed6250ab
Gerrit-Change-Number: 46131
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra aamir.bohra@intel.com
Gerrit-MessageType: newchange



    

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[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer: Add boldar GPIO configuration