[coreboot-gerrit] Change in coreboot[master]: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype

[Subrata Banik (Code Review)]

Attention is currently required from: Tim Crawford, Sean Rhodes, Subrata Banik, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee.
Hello Tim Crawford, Sean Rhodes, Jeremy Soller, Tim Wawrzynczak, Nick Vaccaro, Nick Vaccaro, Eric Lai, Patrick Rudolph, Zhuohao Lee,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/62736

to look at the new patch set (#2).

Change subject: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
......................................................................

{mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype

This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.

This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.

Signed-off-by: Subrata Banik 
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
---
M src/mainboard/google/brya/romstage.c
M src/mainboard/google/deltaur/romstage.c
M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/deltaur/variants/deltan/memory.c
M src/mainboard/google/deltaur/variants/deltaur/memory.c
M src/mainboard/google/volteer/romstage.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/mainboard/intel/shadowmountain/romstage.c
M src/mainboard/intel/tglrvp/romstage_fsp_params.c
M src/mainboard/prodrive/atlas/romstage_fsp_params.c
M src/mainboard/starlabs/labtop/variants/tgl/romstage.c
M src/mainboard/system76/darp7/romstage.c
M src/mainboard/system76/galp5/romstage.c
M src/mainboard/system76/gaze16/romstage.c
M src/mainboard/system76/lemp10/romstage.c
M src/mainboard/system76/oryp8/romstage.c
M src/soc/intel/alderlake/include/soc/meminit.h
M src/soc/intel/alderlake/meminit.c
M src/soc/intel/tigerlake/include/soc/meminit.h
M src/soc/intel/tigerlake/meminit.c
20 files changed, 25 insertions(+), 30 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/62736/2