[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update chip files

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37783 )

Change subject: soc/intel/tigerlake: Update chip files
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Patch Set 30:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/37783/22/src/soc/intel/tigerlake/ch... 
PS22, Line 135: /* Need to update DLL setting to get Emmc running at HS400 speed */
              : 	uint8_t EmmcUseCustomDlls;
              : 	uint32_t EmmcTxCmdDelayRegValue;
              : 	uint32_t EmmcTxDataDelay1RegValue;
              : 	uint32_t EmmcTxDataDelay2RegValue;
              : 	uint32_t EmmcRxCmdDataDelay1RegValue;
              : 	uint32_t EmmcRxCmdDataDelay2RegValue;
              : 	uint32_t EmmcRxStrobeDelayRegValue;
> Just curious: Are you expecting FSP to do different things based on the values that coreboot doesn't […]

No, FSP would be programming the same set of registers. under storage controller init, it would program the platform default anyways, setting the dll tuning from FSP can avoid, setting same registers twice(FSP + Coreboot).

I think we can remove this config for now, if JSL needs to use it for custom DLL tuning then we can add again.