[coreboot-gerrit] Change in coreboot[master]: cse_lite: Move global reset after MRC writeback

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44430 )

Change subject: cse_lite: Move global reset after MRC writeback
......................................................................

cse_lite: Move global reset after MRC writeback

With CSE-lite enabled, we were going through the lengthy memory
training procedure twice on the first power-on boot or after full BIOS
SPI flash update. This moves the global reset performed to achieve the
CSE-lite RO to RW reboot to a later boot phase so that it happens
after the memory training data has been written to the MRC cache. Now,
the 2nd (and subsequent) reboot can utilize the memory training data
established during the 1st boot.

This reduces the first boot time by about 20s on a 16GB system.

Looking at the timing stats form cbmem, the normal boot penalty is
about 300ms - mostly attributed to running FspSiliconInit a 2nd
time. We will get this time back when the mrc_cache refactoring effort
lands (cb:44196, et. al).

BUG=b:162021048
TEST=Booted on volteer, confirmed 20s faster boot time.

Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235
Signed-off-by: Caveh Jalali 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44430
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Nick Vaccaro 
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 5 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Nick Vaccaro: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index c29b56c..a8948be 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -663,7 +663,11 @@
 }

#if CONFIG(SOC_INTEL_TIGERLAKE)
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL);
+/*
+ * This needs to happen after the MRC cache write to avoid a 2nd
+ * memory training sequence.
+ */
+BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL);
 #else
 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL);
 #endif