Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33583 )
Change subject: mb/google/hatch: Do not pull down GPP_F2 internally ......................................................................
mb/google/hatch: Do not pull down GPP_F2 internally
There is already an external pull-up/down resistor tied to this pin to identify if the board is single-channel or dual-channel memory SKU.
BUG=b:135496271 BRANCH=none TEST=build
Signed-off-by: Philip Chen philipchen@google.com Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: David Wu david_wu@quanta.corp-partner.google.com Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved David Wu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 0b66075..e309175 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -284,7 +284,7 @@ /* F1 : WWAN_RESET_1V8_ODL */ PAD_CFG_GPO(GPP_F1, 1, DEEP), /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), /* F3 : GPP_F3 ==> NC */ PAD_NC(GPP_F3, NONE), /* F4 : CNV_BRI_DT */ @@ -460,7 +460,7 @@ /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* F2 : MEM_CH_SEL */ - PAD_CFG_GPI(GPP_F2, DN_20K, PLTRST), + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), /* F11 : PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_F11, NONE, PLTRST), /* F20 : PCH_MEM_STRAP0 */