[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/Kconfig: Create a power restore option

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/25002

Change subject: soc/amd/stoneyridge/Kconfig: Create a power restore option
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soc/amd/stoneyridge/Kconfig: Create a power restore option

File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
that's not used at all and has no control. It's also not used in the
build process. Remove the define from sm.c, create a true Kconfig
definition and use it to define if power should be restored after a power
failure/recovery.

BUG=b:72873003
TEST=Build kahlee. Use serial output to check what is being programmed
to RTC shadow. Build with and without selecting the Kconfig parameter.
Then remove serial output and leave the parameter unselected (always S5
at power recovery).

Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/stoneyridge/Kconfig
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/sm.c
M src/soc/amd/stoneyridge/southbridge.c
4 files changed, 17 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/25002/1

diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index de1cb92..d29846a 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -382,4 +382,11 @@
    int
    default 133

+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+	bool
+	default n
+	help
+	  If selected, after power fail power will be S0 if
+	  previously at S0 else S5.
+
 endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 3011af2..fae3089 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -48,6 +48,10 @@
 #define   PM_SERIRQ_MODE		BIT(6)
 #define   PM_SERIRQ_ENABLE		BIT(7)

+#define PM_RTC_SHADOW			0x5b	/* state when power resumes */
+#define   PM_S5_AT_POWER_RECOVERY	0x04	/* S5 */
+#define   PM_RESTORE_ORIGINAL_POWER	0x07	/* S0 if previouusly at S0 */
+
 #define PM_EVT_BLK			0x60
 #define   WAK_STS			BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
 #define   PCIEXPWAK_STS			BIT(14)
diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c
index 9456cbf..1ea0560 100644
--- a/src/soc/amd/stoneyridge/sm.c
+++ b/src/soc/amd/stoneyridge/sm.c
@@ -32,10 +32,6 @@
 #define MAINBOARD_POWER_OFF 0
 #define MAINBOARD_POWER_ON 1

-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
 /*
 * The southbridge enables all USB controllers by default in SMBUS Control.
 * The southbridge enables SATA by default in SMBUS Control.
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 3d0cc74..ee4b58e 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -545,11 +545,17 @@

void southbridge_final(void *chip_info)
 {
+	uint8_t PM_RESTORED_POWER = PM_S5_AT_POWER_RECOVERY;
+
    if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) {
    	agesawrapper_fchecfancontrolservice();
    	if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE))
    		enable_imc_thermal_zone();
    }
+	if (IS_ENABLED(CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL))
+		PM_RESTORED_POWER = PM_RESTORE_ORIGINAL_POWER;
+	printk(BIOS_DEBUG, "Power control 0x%02x\n", PM_RESTORED_POWER);
+	pm_write8(PM_RTC_SHADOW, PM_RESTORED_POWER);
 }

/*