[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer/elemi: Add memory.c for DDR4

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46378 )

Change subject: mb/google/volteer/elemi: Add memory.c for DDR4
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mb/google/volteer/elemi: Add memory.c for DDR4

Add new memory.c to support DDR4 memory types.

BUG=b:170604353
TEST=emerge-volteer coreboot chromeos-bootimage

Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0
Signed-off-by: Wisley Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378
Tested-by: build bot (Jenkins) 
Reviewed-by: Nick Vaccaro 
---
A src/mainboard/google/volteer/variants/elemi/Makefile.inc
A src/mainboard/google/volteer/variants/elemi/memory.c
2 files changed, 34 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved

diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc
new file mode 100644
index 0000000..9064208
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
diff --git a/src/mainboard/google/volteer/variants/elemi/memory.c b/src/mainboard/google/volteer/variants/elemi/memory.c
new file mode 100644
index 0000000..d3de4be
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/elemi/memory.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+/*This mb_ddr4_cfg structure is intentionally left empty so that fields are left nil. */
+static const struct mb_ddr4_cfg elemi_memcfg = {
+};
+
+static const struct ddr_memory_cfg baseboard_memcfg = {
+	.mem_type = MEMTYPE_DDR4,
+	.ddr4_cfg = &elemi_memcfg
+};
+
+const struct ddr_memory_cfg *variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	gpio_t spd_gpios[] = {
+		GPIO_MEM_CONFIG_3,
+		GPIO_MEM_CONFIG_2,
+		GPIO_MEM_CONFIG_1,
+		GPIO_MEM_CONFIG_0,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}