Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45713 )
Change subject: sb/intel/lynxpoint/pcie: Fix clock gating routine ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45713/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45713/1//COMMIT_MSG@7 PS1, Line 7: sb/intel/lynxpoint/pcie.c: Fix subtle blunder
Please just rewrite both, e.g. […]
Done, and confirmed that the bit indeed needs to be set.
https://review.coreboot.org/c/coreboot/+/45713/2/src/southbridge/intel/lynxp... File src/southbridge/intel/lynxpoint/pcie.c:
https://review.coreboot.org/c/coreboot/+/45713/2/src/southbridge/intel/lynxp... PS2, Line 286: pci_or_config8(dev, 0x324, 1 << 5);
If it wasn't changing anything, the commit message would be a lie ;)
Yes, it is intentional. The original code was wrong, and the new code matches what the BWG states.