[coreboot-gerrit] Change in coreboot[master]: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40917 )

Change subject: mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M
......................................................................

Patch Set 2: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/40917/2/src/mainboard/intel/cedaris... 
File src/mainboard/intel/cedarisland_crb/romstage.c:

https://review.coreboot.org/c/coreboot/+/40917/2/src/mainboard/intel/cedaris... 
PS2, Line 13: 	write8(start + 140, 0x1d);
That's an interesting way of setting FSP parameters. Any reason as to why it's being done this way?