[coreboot-gerrit] Change in coreboot[master]: sc7180: enable bl31

[mturney mturney (Code Review)]

Hello [e-mail],

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/35504

to review the following change.

Change subject: sc7180: enable bl31
......................................................................

sc7180: enable bl31

Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/28014/44

Change-Id: Ia961ee0e30478e21fd786ce464655977449df510
Signed-off-by: ashk 
---
M src/soc/qualcomm/sc7180/Kconfig
M src/soc/qualcomm/sc7180/include/soc/memlayout.ld
2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35504/1

diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig
index df5d116..28f7522 100644
--- a/src/soc/qualcomm/sc7180/Kconfig
+++ b/src/soc/qualcomm/sc7180/Kconfig
@@ -6,6 +6,7 @@
    select ARCH_RAMSTAGE_ARMV8_64
    select ARCH_ROMSTAGE_ARMV8_64
    select ARCH_VERSTAGE_ARMV8_64
+	select ARM64_USE_ARM_TRUSTED_FIRMWARE
    select GENERIC_GPIO_LIB
    select GENERIC_UDELAY
    select HAVE_MONOTONIC_TIMER
diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
index f4e6f05..e47f881 100644
--- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld
@@ -72,7 +72,7 @@
    REGION(dram_reserved1, 0x80820000, 0x20000, 0x1000)
    REGION(dram_reserved, 0x80900000, 0x200000, 0x1000)
    /* Various hardware/software subsystems make use of this area */
-	BL31(0x85000000, 0x1A800000)
+	BL31(0x80C00000, 0x1A800000)
    POSTRAM_CBFS_CACHE(0x9F800000, 384K)
    RAMSTAGE(0x9F860000, 2M)
 }