[coreboot-gerrit] [M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

[Paul Menzel (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Eric Lai, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas.

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 )

Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
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Patch Set 23: Code-Review+1

(1 comment)

File src/mainboard/intel/mtlrvp/romstage.c:

https://review.coreboot.org/c/coreboot/+/66190/comment/e23a221f_3b504b6b 
PS22, Line 45:
> @Paul, do you still see issue here?

Thank you for addressing my comment. If you address comments, you can mark the comments as resolved yourself.