[coreboot-gerrit] Change in coreboot[master]: [under test]mb/google/hatch: Program gpio clk power gating settings i...

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37865 )

Change subject: [under test]mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0
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[under test]mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0

With PchPmSlpS0Vm075VSupport FSP UPD set, SoC requires gpio clk to be
power gated.
But when gpio clk is power gated, it requires longer interrupt
assertion from device.

This commit provides a way to set gpio clk power gating settings in
SPIO PS0/PS3 so that cr50 doesn't need longer interrupt assertion
and SoC can still enter runtime s0ix with PchPmSlpS0Vm075VSupport set.

BUG=:141831197

Change-Id: I33a3d5897ec40afee29759160963363c322d5ad0
Signed-off-by: Kane Chen 
---
M src/mainboard/google/hatch/mainboard.asl
1 file changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37865/1

diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl
index dff1a75..db3c7ff 100644
--- a/src/mainboard/google/hatch/mainboard.asl
+++ b/src/mainboard/google/hatch/mainboard.asl
@@ -55,3 +55,17 @@
    	LOCL (0)
    }
 }
+
+Scope (_SB.PCI0.SPI0)
+{
+	Method (_PS0, 0)
+	{
+		LOCL (0)
+	}
+
+	Method(_PS3, 0)
+	{
+		LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	}
+
+}