[coreboot-gerrit] [S] Change in coreboot[main]: soc/amd/phoenix: add openSIL calls

[Felix Held (Code Review)]

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80296?usp=email )

Change subject: soc/amd/phoenix: add openSIL calls
......................................................................

soc/amd/phoenix: add openSIL calls

Add the calls to the openSIL stubs to do the silicon initialization, to
get the APCI IO ports, and to get the memory map.

Signed-off-by: Felix Held 
Change-Id: I6f37bf211e130cb44927f8a0e7f9134d246dfc1c
---
M src/soc/amd/phoenix/acpi.c
M src/soc/amd/phoenix/chip.c
M src/soc/amd/phoenix/memmap.c
3 files changed, 20 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/80296/1

diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index a6482ee..606a45f 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -19,6 +19,7 @@
 #include <device/device.h>
 #include <soc/iomap.h>
 #include <types.h>
+#include <vendorcode/amd/opensil/genoa_poc/opensil.h>
 #include "chip.h"

/*
@@ -29,12 +30,17 @@
 {
    const struct soc_amd_phoenix_config *cfg = config_of_soc();

-	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
+	if (CONFIG(PLATFORM_USES_FSP2_0)) {
+		printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);

-	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
-	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
-	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
-	fadt->gpe0_blk = ACPI_GPE0_BLK;
+		fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+		fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+		fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
+		fadt->gpe0_blk = ACPI_GPE0_BLK;
+	} else {
+		/* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */
+		opensil_fill_fadt_io_ports(fadt);
+	}

fadt->pm1_evt_len = 4;	/* 32 bits */
    fadt->pm1_cnt_len = 2;	/* 16 bits */
diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c
index 2291945..a9b0e57 100644
--- a/src/soc/amd/phoenix/chip.c
+++ b/src/soc/amd/phoenix/chip.c
@@ -12,6 +12,7 @@
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include <types.h>
+#include <vendorcode/amd/opensil/stub/opensil.h>
 #include "chip.h"

static const char *soc_acpi_name(const struct device *dev)
@@ -39,8 +40,12 @@
 {
    default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;

-	if (CONFIG(PLATFORM_USES_FSP2_0))
+	if (CONFIG(PLATFORM_USES_FSP2_0)) {
    	amd_fsp_silicon_init();
+	} else {
+		setup_opensil();
+		opensil_xSIM_timepoint_1();
+	}

data_fabric_set_mmio_np();

diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c
index 432d850..e516572 100644
--- a/src/soc/amd/phoenix/memmap.c
+++ b/src/soc/amd/phoenix/memmap.c
@@ -7,6 +7,7 @@
 #include <cbmem.h>
 #include <device/device.h>
 #include <stdint.h>
+#include <vendorcode/amd/opensil/stub/opensil.h>

/*
  *                     +--------------------------------+
@@ -96,4 +97,6 @@

if (CONFIG(PLATFORM_USES_FSP2_0))
    	read_fsp_resources(dev, idx);
+	else
+		add_opensil_memmap(dev, idx);
 }