[coreboot-gerrit] Change in coreboot[master]: mb/google/guybrush: Add variant_espi_gpio_table

[Rob Barnes (Code Review)]

Attention is currently required from: Julius Werner, Yu-Ping Wu.
Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59082 )

Change subject: mb/google/guybrush: Add variant_espi_gpio_table
......................................................................

mb/google/guybrush: Add variant_espi_gpio_table

Add separate gpio table for eSPI bus.

BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush

Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8
Signed-off-by: Rob Barnes 
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/verstage.c
M src/security/vboot/vboot_common.h
4 files changed, 65 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/59082/1

diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 66b40be..7bd392f 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -234,6 +234,23 @@
    PAD_GPI(GPIO_91, PULL_NONE),
 };

+static const struct soc_amd_gpio espi_gpio_table[] = {
+	/* ESPI_CS_L */
+	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
+	/* ESPI_SOC_CLK */
+	PAD_NF(GPIO_86, SPI_CLK, PULL_NONE),
+	/* ESPI1_DATA0 */
+	PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
+	/* ESPI1_DATA1 */
+	PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
+	/* ESPI1_DATA2 */
+	PAD_NF(GPIO_106, SPI2_WP_L_ESPI2_D2, PULL_NONE),
+	/* ESPI1_DATA3 */
+	PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
+	/* ESPI_ALERT_L */
+	PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
+};
+
 /* Power-on timing requirements:
  * Fibocom 350-GL:
  *   FCP0# goes high (GPIO 6)	to	Reset# high (GPIO 24):	20ms min
@@ -374,6 +391,12 @@
    return fpmcu_disable_gpio_table;
 }

+const __weak struct soc_amd_gpio *variant_espi_gpio_table(size_t *size)
+{
+	*size = ARRAY_SIZE(espi_gpio_table);
+	return espi_gpio_table;
+}
+
 __weak void variant_fpmcu_reset(void)
 {
    size_t size;
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index 6cc96f8..0ebc59a 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -46,6 +46,9 @@
 /* This function provides GPIO settings for fpmcu disable. */
 const struct soc_amd_gpio *variant_fpmcu_disable_gpio_table(size_t *size);

+/* This function provides GPIO settings for eSPI bus. */
+const struct soc_amd_gpio *variant_espi_gpio_table(size_t *size);
+
 /* Finalize GPIOs, such as FPMCU power */
 void variant_finalize_gpios(void);

diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c
index e6434df..163caeb 100644
--- a/src/mainboard/google/guybrush/verstage.c
+++ b/src/mainboard/google/guybrush/verstage.c
@@ -21,24 +21,47 @@
    }
 }

+
+/*
+* TODO : Make common function in cezanne code and just call it
+* when PCI access is fixed in the PSP (b/186602472).
+* For now the PSP doesn't configure LPC so it should be fine.
+*/
+static void setup_espi_mux(void)
+{
+	uint32_t dword;
+
+	if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
+		return;
+
+	printk(BIOS_DEBUG, "Verstage configure eSPI\n");
+
+	dword = pm_io_read32(PM_SPI_PAD_PU_PD);
+	dword |= PM_ESPI_CS_USE_DATA2;
+	pm_io_write32(PM_SPI_PAD_PU_PD, dword);
+
+	dword = pm_io_read32(PM_ACPI_CONF);
+	dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL;
+	pm_io_write32(PM_ACPI_CONF, dword);
+}
+
 void verstage_mainboard_early_init(void)
 {
    setup_gpio();

-	/*
-	 * TODO : Make common function in cezanne code and just call it
-	 * when PCI access is fixed in the PSP (b/186602472).
-	 * For now the PSP doesn't configure LPC so it should be fine.
-	 */
-	if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) {
-		uint32_t dword;
-		printk(BIOS_DEBUG, "Verstage configure eSPI\n");
-		dword = pm_io_read32(PM_SPI_PAD_PU_PD);
-		dword |= PM_ESPI_CS_USE_DATA2;
-		pm_io_write32(PM_SPI_PAD_PU_PD, dword);
+	setup_espi_mux();
+}

-		dword = pm_io_read32(PM_ACPI_CONF);
-		dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL;
-		pm_io_write32(PM_ACPI_CONF, dword);
-	}
+void verstage_mainboard_espi_init(void)
+{
+	const struct soc_amd_gpio *gpios;
+	size_t num_gpios;
+
+	if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
+		return;
+
+	gpios = variant_espi_gpio_table(&num_gpios);
+	gpio_configure_pads(gpios, num_gpios);
+
+	setup_espi_mux();
 }
diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h
index 512da0e..d7b549c 100644
--- a/src/security/vboot/vboot_common.h
+++ b/src/security/vboot/vboot_common.h
@@ -43,6 +43,7 @@
  */
 void verstage_main(void);
 void verstage_mainboard_early_init(void);
+void verstage_mainboard_espi_init(void);
 void verstage_mainboard_init(void);

/* Check boot modes */