[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: disable_l2c_sram in ramstage

[Yidi Lin (Code Review)]

Hello CK HU,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/46387

to review the following change.

Change subject: soc/mediatek/mt8192: disable_l2c_sram in ramstage
......................................................................

soc/mediatek/mt8192: disable_l2c_sram in ramstage

Signed-off-by: CK Hu 
Change-Id: Icaf80bd9da3e082405ba66ef05dd5ea9185784a0
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/mmu_operations.c
M src/soc/mediatek/mt8192/soc.c
3 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46387/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 8bc7b74..891d38a 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -33,6 +33,7 @@
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-y += emi.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
+ramstage-y += ../common/mmu_operations.c mmu_operations.c
 ramstage-y += ../common/mtcmos.c mtcmos.c
 ramstage-y += soc.c
 ramstage-y += ../common/timer.c
diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c
new file mode 100644
index 0000000..fb3620e
--- /dev/null
+++ b/src/soc/mediatek/mt8192/mmu_operations.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <soc/mcucfg.h>
+#include <soc/mmu_operations.h>
+
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
+DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
+
+void mtk_soc_disable_l2c_sram(void)
+{
+	unsigned long v;
+
+	SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
+	dsb();
+
+	__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
+	v |= (0xf << 4);
+	__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
+	dsb();
+
+	do {
+		__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
+	} while (((v >> 0x4) & 0xf) != 0xf);
+
+	SET32_BITFIELDS(&mt8192_mcucfg->mp0_cluster_cfg0,
+			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
+	dsb();
+}
diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c
index 9850fa6..6978406 100644
--- a/src/soc/mediatek/mt8192/soc.c
+++ b/src/soc/mediatek/mt8192/soc.c
@@ -2,6 +2,7 @@

#include <device/device.h>
 #include <soc/emi.h>
+#include <soc/mmu_operations.h>
 #include <symbols.h>

static void soc_read_resources(struct device *dev)
@@ -11,6 +12,7 @@

static void soc_init(struct device *dev)
 {
+	mtk_mmu_disable_l2c_sram();
 }

static struct device_operations soc_ops = {