[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Allow fine grained control of S0iX states

[Jes Klinke (Code Review)]

Hello Jes Klinke,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44355

to review the following change.

Change subject: soc/intel/tigerlake: Allow fine grained control of S0iX states
......................................................................

soc/intel/tigerlake: Allow fine grained control of S0iX states

Expose FSP parameter to enable/disable each individual substate.

See https://review.coreboot.org/c/coreboot/+/43741 for context.

Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7
Signed-off-by: [e-mail]
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/44355/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index dc910ff..6c5daa5 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -78,6 +78,9 @@

/* Enable S0iX support */
    int s0ix_enable;
+	/* S0iX: Selectively enable individual sub-states */
+	uint8_t LpmStateEnableMask;
+
    /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
    uint8_t TcssD3HotDisable;
    /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index a61a025..53ca11e 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -204,6 +204,13 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* S0iX: Selectively enable individual sub-states.
+	 *
+	 * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
+	 * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4
+	 */
+	params->LpmStateEnableMask = config->LpmStateEnableMask;
+
    /*
     * Power Optimizer for DMI and SATA.
     * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0.