[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Fix description of auto-precharge bit

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50473 )

Change subject: nb/intel/sandybridge: Fix description of auto-precharge bit
......................................................................

nb/intel/sandybridge: Fix description of auto-precharge bit

This bit is primarily used to issue RDA commands. There doesn't seem to
be any limitation regarding the number of address bits.

Change-Id: I2804f67319c9bc736f9086af408853056aabedd6
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/registers/mchbar.h
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/50473/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index cef0131..8e54101 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1712,7 +1712,7 @@
    				.rank    = slotrank,
    			},
    		},
-			/* DRAM command RD */
+			/* DRAM command RDA */
    		[2] = {
    			.sp_cmd_ctrl = {
    				.command    = IOSAV_RD,
diff --git a/src/northbridge/intel/sandybridge/registers/mchbar.h b/src/northbridge/intel/sandybridge/registers/mchbar.h
index 2fe6b24..6adf428 100644
--- a/src/northbridge/intel/sandybridge/registers/mchbar.h
+++ b/src/northbridge/intel/sandybridge/registers/mchbar.h
@@ -112,7 +112,7 @@
  *          end architecture RTL;
  *
  *   [16]       Chip Select mode control.
- *   [17]       Auto Precharge. Only valid when using 10 row bits!
+ *   [17]       Auto Precharge. Used to send RDA commands.
  *
  * IOSAV_n_SUBSEQ_CTRL_ch(channel, index)
  *   The parameters of the subseq: number of repetitions of the command,