[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint: Use common AHCI library

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47095 )

Change subject: sb/intel/lynxpoint: Use common AHCI library
......................................................................

sb/intel/lynxpoint: Use common AHCI library

This avoids confusing and potentially dangerous pointer arithmetics.
Behaviour before after this patch should be equivalent, too.

Change-Id: I62a26d74fe78dc0158b383da9126c56746722c53
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/lynxpoint/sata.c
1 file changed, 39 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47095/1

diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index d8eb2a8..e4aa083 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -7,6 +7,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <delay.h>
+#include <southbridge/intel/common/ahci.h>
 #include "chip.h"
 #include "iobp.h"
 #include "pch.h"
@@ -37,8 +38,6 @@
 {
    u32 reg32;

-	u32 *abar;
-
    /* Get the chip configuration */
    config_t *config = dev->chip_info;

@@ -51,7 +50,7 @@

/* SATA configuration */

-	/* Enable memory space decoding for ABAR */
+	/* Enable memory space decoding for AHCI BAR */
    pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);

printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
@@ -107,31 +106,47 @@
    pci_write_config32(dev, 0x94, reg32);

/* Initialize AHCI memory-mapped space */
-	abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-	printk(BIOS_DEBUG, "ABAR: %p\n", abar);
-	/* CAP (HBA Capabilities) : enable power management */
-	reg32 = read32(abar + 0x00);
-	reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
-	reg32 &= ~0x00020060; // clear SXS+EMS+PMS
+	const uintptr_t ahci_bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+	printk(BIOS_DEBUG, "AHCI BAR: %p\n", (void *)ahci_bar);
+
+	union ahci_reg_cap ahci_cap = {
+		.raw = ahci_read32(ahci_bar, AHCI_REG_CAP),
+	};
+
+	ahci_cap.external_sata        = 0; /* Should be configurable */
+	ahci_cap.enclosure_management = 0;
+	ahci_cap.port_multiplier      = 0;
+
+	ahci_cap.partial_state        = 1;
+	ahci_cap.slumber_state        = 1;
+	ahci_cap.aggressive_link_pm   = 1;
+	ahci_cap.staggered_spinup     = 1;
+
    if (pch_is_lp())
-		reg32 |= (1 << 18);   // SAM: SATA AHCI MODE ONLY
-	write32(abar + 0x00, reg32);
-	/* PI (Ports implemented) */
-	write32(abar + 0x03, config->sata_port_map);
-	(void)read32(abar + 0x03); /* Read back 1 */
-	(void)read32(abar + 0x03); /* Read back 2 */
-	/* CAP2 (HBA Capabilities Extended)*/
-	reg32 = read32(abar + 0x09);
-	/* Enable DEVSLP */
+		ahci_cap.ahci_mode_only = 1;
+
+	ahci_write32(ahci_bar, AHCI_REG_CAP, ahci_cap.raw);
+
+	ahci_write_ports_implemented(ahci_bar, config->sata_port_map);
+
+	union ahci_reg_cap_2 ahci_cap_2 = {
+		.raw = ahci_read32(ahci_bar, AHCI_REG_CAP_2),
+	};
+
    if (pch_is_lp()) {
-		if (config->sata_devslp_disable)
-			reg32 &= ~(1 << 3);
-		else
-			reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
+		if (config->sata_devslp_disable) {
+			ahci_cap_2.supports_device_sleep = 0;
+		} else {
+			ahci_cap_2.auto_partial_to_slumber   = 1;
+			ahci_cap_2.supports_device_sleep     = 1;
+			ahci_cap_2.aggressive_devslp_mgmt    = 1;
+			ahci_cap_2.devslp_entry_slumber_only = 1;
+		}
    } else {
-		reg32 &= ~0x00000002;
+		ahci_cap_2.nvm_hci_present = 0;
    }
-	write32(abar + 0x09, reg32);
+
+	ahci_write32(ahci_bar, AHCI_REG_CAP_2, ahci_cap_2.raw);

/* Set Gen3 Transmitter settings if needed */
    if (config->sata_port0_gen3_tx)