[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38514 )

Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet
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Patch Set 4:

Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/280
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/279
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/278

Please note: This test is under development and might not be accurate at all!