Hello Werner Zeh, Patrick Rudolph, Felix Held, Mario Scheithauer, David Hendricks, Paul Menzel, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34173
to look at the new patch set (#6).
Change subject: sb/intel/common/spi: Increase flash erase timeout ......................................................................
sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms ->1s) for SPI HW-sequencing flash erase operations. Without that the erase for MRC cache writing on siemens/mc_bdx1 sometimes goes wrong because the timeout stops waiting for flash cycle completion. It was found during continuous integration. Investigation showed that the used flash type takes sporadic (e.g. 5% of the test cycles) more time for completion of erasing operation if the ambient temperature increases. The measured time values are in range of data sheet of SPI flash. 60ms is a typical value. So increasing the value is necessary.
tested on siemens/bdx1; measured time values with increased ambient temperature of flash were always smaller than worst case value of 1s.
Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2 Signed-off-by: Uwe Poeche uwe.poeche@siemens.com --- M src/southbridge/intel/common/spi.c 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34173/6