Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41949 )
Change subject: soc/mediatek/mt8183: Support 6GB, 8GB DDR bootup ......................................................................
Patch Set 8:
(6 comments)
https://review.coreboot.org/c/coreboot/+/41949/4/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/41949/4/src/soc/mediatek/mt8183/dra... PS4, Line 134: u16
Shouldn't the local variable 'value' be defined to be 'u16' instead of 'u8'? Then we can change the […]
Done
https://review.coreboot.org/c/coreboot/+/41949/8/src/soc/mediatek/mt8183/dra... File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:
https://review.coreboot.org/c/coreboot/+/41949/8/src/soc/mediatek/mt8183/dra... PS8, Line 2735: max_density = density;
Please print a warning in this case.
It's just updating max_density, not an unexpected situation.
https://review.coreboot.org/c/coreboot/+/41949/4/src/soc/mediatek/mt8183/emi... File src/soc/mediatek/mt8183/emi.c:
https://review.coreboot.org/c/coreboot/+/41949/4/src/soc/mediatek/mt8183/emi... PS4, Line 326: 101
This value won't be used anywhere.
Done
https://review.coreboot.org/c/coreboot/+/41949/4/src/soc/mediatek/mt8183/emi... PS4, Line 389: dramc_dbg
Forgot to change this?
Done
https://review.coreboot.org/c/coreboot/+/41949/4/src/soc/mediatek/mt8183/emi... PS4, Line 393: rf_cab_opt[freq_group][rfcab_grp]
Forgot to change this?
Done
https://review.coreboot.org/c/coreboot/+/41949/4/src/soc/mediatek/mt8183/inc... File src/soc/mediatek/mt8183/include/soc/dramc_param.h:
https://review.coreboot.org/c/coreboot/+/41949/4/src/soc/mediatek/mt8183/inc... PS4, Line 68: DQS_NUMBER
the MT8183 SOC also support LPDDR3 DDR, DQS_NUMBER of LP3 is 4 and DQS_NUMBER of the LP4X is 2. […]
If we follow Hung-Te's suggestion above and keep dramc_param.h unchanged, then we won't have to do it.