[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add DDR4 mem configuration

[Srinidhi N Kaushik (Code Review)]

Hello Raj Astekar, Patrick Rudolph, Subrata Banik, Nick Vaccaro, Wonkyu Kim, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39040

to look at the new patch set (#6).

Change subject: soc/intel/tigerlake: add DDR4 mem configuration
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soc/intel/tigerlake: add DDR4 mem configuration

Add functions in meminit to support DDR4 memory configuration.

BUG=none
BRANCH=none
TEST= build tglrvp with DDR4 mem type flash and boot to kernel

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I3858cc56c838862fc61123c8b7dba11dbc40983c
---
M src/soc/intel/tigerlake/include/soc/meminit_tgl.h
M src/soc/intel/tigerlake/meminit_tgl.c
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/39040/6