[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Drop unreferenced devicetree settings

[Angel Pons (Code Review)]

Hello  Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48566

to review the following change.

Change subject: soc/intel/alderlake: Drop unreferenced devicetree settings
......................................................................

soc/intel/alderlake: Drop unreferenced devicetree settings

No mainboard uses these settings, nor does SoC code. Drop them.

Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa
Signed-off-by: Angel Pons 
---
M src/soc/intel/alderlake/chip.h
1 file changed, 0 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48566/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 428fd4d..38d9671 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -146,12 +146,6 @@
    /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
    uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];

-	/* Integrated Sensor */
-	uint8_t PchIshEnable;
-
-	/* Heci related */
-	uint8_t Heci3Enabled;
-
    /* Gfx related */
    enum {
    	IGD_SM_0MB = 0x00,
@@ -178,8 +172,6 @@
    uint8_t InternalGfx;
    uint8_t SkipExtGfxScan;

-	uint32_t GraphicsConfigPtr;
-
    /* HeciEnabled decides the state of Heci1 at end of boot
     * Setting to 0 (default) disables Heci1 and hides the device from OS */
    uint8_t HeciEnabled;