Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36551 )
Change subject: soc/intel/tigerlake/include: Include headers from soc/intel/icelake ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/36551/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36551/1//COMMIT_MSG@16 PS1, Line 16: 5. Add CPU/PCH/SA EDS docuemnt number and chapter number document
https://review.coreboot.org/c/coreboot/+/36551/1//COMMIT_MSG@18 PS1, Line 18: Tiger Lake specific changes will follow in subsequent patches. are those patchsets public yet?
https://review.coreboot.org/c/coreboot/+/36551/1/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio.h:
https://review.coreboot.org/c/coreboot/+/36551/1/src/soc/intel/tigerlake/inc... PS1, Line 19: * Chapter number: 27 the datasheet holds a CROS_GPIO device name?
https://review.coreboot.org/c/coreboot/+/36551/1/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/36551/1/src/soc/intel/tigerlake/inc... PS1, Line 22: #define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS where are those address taken from?