Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33775 )
Change subject: arch/x86: Adjust size of postcar stack ......................................................................
arch/x86: Adjust size of postcar stack
With VBOOT=y && VBOOT_MEASURED_BOOT=y message digest will be allocated from the stack and 1 KiB reserve used with the recent platforms was no longer sufficient.
The comment of LZMA scratchpad consuming stack was obsolete for postcar, so these can be reduced to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar_loader.c M src/cpu/intel/haswell/romstage.c M src/drivers/intel/fsp1_1/car.c M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/i440bx/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/nehalem/ram_calc.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/sandybridge/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 23 files changed, 42 insertions(+), 55 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Werner Zeh: Looks good to me, approved
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 75f1f43..38066c1 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -309,8 +309,9 @@ };
/* - * Initialize postcar_frame object allocating stack size in cbmem - * with the provided size. Returns 0 on success, < 0 on error. + * Initialize postcar_frame object allocating stack from cbmem, + * with stack_size == 0, default 4 KiB is allocated. + * Returns 0 on success, < 0 on error. */ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 732b767..35e139f 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -48,6 +48,15 @@ { void *stack;
+ /* + * Use default postcar stack size of 4 KiB. This value should + * not be decreased, because if mainboards use vboot, 1 KiB will + * not be enough anymore. + */ + + if (stack_size == 0) + stack_size = 4 * KiB; + stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, stack_size); if (stack == NULL) { printk(BIOS_ERR, "Couldn't add %zd byte stack in cbmem.\n", diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 3cbdf44..47b9976 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -38,8 +38,6 @@ #include <cpu/intel/romstage.h> #include "haswell.h"
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -48,7 +46,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 84ea7d1..1e89a8e 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -25,8 +25,6 @@ #include <program_loading.h> #include <timestamp.h>
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -35,7 +33,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index e1d4f62..6b1883c 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <arch/cpu.h> #include <stdint.h> #include <cbmem.h> #include <console/console.h> @@ -31,11 +32,7 @@
timestamp_add_now(TS_START_ROMSTAGE);
- /** - * The LZMA decoder needs about 4 KiB stack. - * Leave 1 KiB stack for general postcar code. - */ - if (postcar_frame_init(&pcf, 5 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/** diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 3e0870f..e409ad1 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <arch/cpu.h> #include <stdint.h> #include <cbmem.h> #include <console/console.h> @@ -32,11 +33,7 @@
timestamp_add_now(TS_START_ROMSTAGE);
- /** - * The LZMA decoder needs about 4 KiB stack. - * Leave 1 KiB stack for general postcar code. - */ - if (postcar_frame_init(&pcf, 5 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/** diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index f7a08bc..d450065 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -35,8 +35,6 @@ return (void *)tolm; }
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -45,7 +43,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c1307c4..c614082 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -123,8 +123,6 @@ return (void *) top_of_ram; }
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -133,7 +131,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index 09a3b03..495ca86 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -15,6 +15,7 @@
#define __SIMPLE_DEVICE__
+#include <arch/cpu.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> @@ -67,8 +68,6 @@ return (void *)tom; }
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -77,7 +76,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 752c8f9..525a5b9 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -88,8 +88,6 @@ return ggc2uma[gms] << 10; }
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -98,7 +96,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index e32190f..ba37610 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -43,8 +43,6 @@ return (void *) smm_region_start(); }
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -53,7 +51,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index a789956..d1b43aa 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -16,6 +16,7 @@
#define __SIMPLE_DEVICE__
+#include <arch/cpu.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> @@ -137,8 +138,6 @@
}
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -147,7 +146,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 5cda8a3..343ae62 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -43,8 +43,6 @@ return (void *) smm_region_start(); }
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -53,7 +51,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */ diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 3714969..be9c10f 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -134,8 +134,6 @@ return (void *) top_of_ram; }
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -144,7 +142,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 12ee2a8..000d100 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -153,7 +153,7 @@ printk(BIOS_ERR, "Failed to set romstage handoff data\n");
post_code(0x44); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 5bf501d..5d65a00 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -240,7 +240,7 @@ else printk(BIOS_ERR, "Failed to determine variable data\n");
- if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
mainboard_save_dimm_info(); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 5621dd1..7e2bb64 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -238,8 +238,6 @@ romstage_handoff_init(prev_sleep_state == ACPI_S3); }
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ static void platform_enter_postcar(void) @@ -247,7 +245,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 9bca716..9c86809 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,6 +16,7 @@ #include <stddef.h> #include <stdint.h> #include <arch/cbfs.h> +#include <arch/cpu.h> #include <bootblock_common.h> #include <bootmode.h> #include <cbmem.h> @@ -34,8 +35,6 @@ #include <soc/romstage.h> #include <soc/spi.h>
-#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ @@ -44,7 +43,7 @@ struct postcar_frame pcf; uintptr_t top_of_ram;
- if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9dadb2d..94b9899 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <arch/cpu.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> @@ -146,7 +147,7 @@ pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 4477c92..6d8eaab 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <arch/cpu.h> #include <arch/io.h> #include <cbmem.h> #include <cf9_reset.h> @@ -161,7 +162,7 @@ display_fsp_smbios_memory_info_hob(); #endif
- if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index b0eeb2e..514e5e8 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <arch/cpu.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> @@ -131,7 +132,7 @@ pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1 * KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 5ebbacb..a8bd26e 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <arch/cpu.h> #include <arch/symbols.h> #include <console/console.h> #include <cbmem.h> @@ -61,7 +62,7 @@ /* Initialize the PCIe bridges */ pcie_init();
- if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/* Locate the top of RAM */ diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 6ff59ba..fafa343 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -158,7 +158,7 @@ pmc_set_disb(); if (!s3wake) save_dimm_info(); - if (postcar_frame_init(&pcf, 1*KiB)) + if (postcar_frame_init(&pcf, 0)) die("Unable to initialize postcar frame.\n");
/*