[coreboot-gerrit] Change in coreboot[master]: reset: Declare new single-function reset API

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29047

Change subject: reset: Declare new single-function reset API
......................................................................

reset: Declare new single-function reset API

board_reset() replaces the existing common reset API. There is no common
distinction between reset types across platforms, hence, common code
could never decide which one to call.

Currently only hard_reset() is used by common code. We'll replace these
calls after moving all implementations to the new API.

Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128
Signed-off-by: Nico Huber 
---
M src/include/reset.h
M src/lib/Kconfig
M src/lib/reset.c
3 files changed, 58 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29047/1

diff --git a/src/include/reset.h b/src/include/reset.h
index cf9d574..47e71f0 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -1,7 +1,46 @@
 #ifndef RESET_H
 #define RESET_H

-/* Generic reset functions. Call from code that wants to trigger a reset. */
+/*
+ * Generic board reset function. Call from common code that
+ * wants to trigger a reset.
+ */
+__noreturn void board_reset(void);
+/*
+ * SoC or board specific implementation of the board reset.
+ *
+ * Implementations should perform a warm reset if the following
+ * criteria can be met:
+ *
+ *   o For vboot support, the TPM MUST be reset.
+ *
+ *   o All SoC/chipset blocks SHOULD be reset except for those
+ *     that are intentionally meant to survive reset (e.g. tomb-
+ *     stone registers and that sort of stuff).
+ *
+ *   o All external SoC pins MUST return to power-on reset values.
+ *
+ *   o The CPU MUST resume execution from power-on reset vector
+ *     (same as cold boot).
+ *
+ *   o Other board components (e.g. PCI, SDIO and stuff) SHOULD
+ *     be reset.
+ *
+ *   o USB SHOULD be power-cycled.
+ *
+ *   o Board components that are intended to be fully independent
+ *     from SoC (e.g. EC and EC-attached devices, the Cr50 on
+ *     Chromebooks) SHOULD NOT be reset.
+ *
+ * Otherwise a cold boot should be initiated.
+ *
+ * General recommendations:
+ *
+ *   o DRAM SHOULD NOT lose power if possible.
+ *
+ *   o Reset time SHOULD be minimized
+ */
+void do_board_reset(void);

/* Super-hard reset specific to some Intel SoCs. */
 __noreturn void global_reset(void);
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index eb4c16e..fcad921 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -1,3 +1,6 @@
+config MISSING_BOARD_RESET
+	bool
+
 config NO_EDID_FILL_FB
    bool
    default y if !MAINBOARD_DO_NATIVE_VGA_INIT
diff --git a/src/lib/reset.c b/src/lib/reset.c
index d828421..9c47adf 100644
--- a/src/lib/reset.c
+++ b/src/lib/reset.c
@@ -18,6 +18,21 @@
 #include <halt.h>
 #include <reset.h>

+__noreturn void board_reset(void)
+{
+	printk(BIOS_INFO, "%s() called!\n", __func__);
+	dcache_clean_all();
+	do_board_reset();
+	halt();
+}
+
+#if IS_ENABLED(CONFIG_MISSING_BOARD_RESET)
+void do_board_reset(void)
+{
+	printk(BIOS_CRIT, "No board_reset implementation, hanging...\n");
+}
+#endif
+
 __noreturn static void __hard_reset(void) {
    if (IS_ENABLED(CONFIG_HAVE_HARD_RESET))
    	do_hard_reset();