Attention is currently required from: Felix Singer, Michał Żygowski, Michael Niewöhner. Hello Michał Żygowski,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62498
to review the following change.
Change subject: mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support ......................................................................
mb/clevo/tgl-u: Add Clevo NV41 Tiger Lake laptop support
Signed-off-by: Michał Kopeć michal.kopec@3mdeb.com Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ib373d62d9d18bafdfde2e1acb4e00e3a20ae09bc --- A configs/config.clevo_nv4x M src/ec/clevo/it5570/acpi/ec_ram.asl A src/mainboard/clevo/tgl-u/Kconfig A src/mainboard/clevo/tgl-u/Kconfig.name A src/mainboard/clevo/tgl-u/Makefile.inc A src/mainboard/clevo/tgl-u/acpi/mainboard.asl A src/mainboard/clevo/tgl-u/acpi/sleep.asl A src/mainboard/clevo/tgl-u/board.fmd A src/mainboard/clevo/tgl-u/board_info.txt A src/mainboard/clevo/tgl-u/bootblock.c A src/mainboard/clevo/tgl-u/cmos.default A src/mainboard/clevo/tgl-u/cmos.layout A src/mainboard/clevo/tgl-u/dsdt.asl A src/mainboard/clevo/tgl-u/mainboard.c A src/mainboard/clevo/tgl-u/memory.c A src/mainboard/clevo/tgl-u/romstage.c A src/mainboard/clevo/tgl-u/smihandler.c A src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb A src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h A src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h A src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc A src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt A src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt A src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c A src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c A src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb A src/mainboard/clevo/tgl-u/vboot-rwa.fmd 27 files changed, 1,242 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62498/1
diff --git a/configs/config.clevo_nv4x b/configs/config.clevo_nv4x new file mode 100644 index 0000000..020973b --- /dev/null +++ b/configs/config.clevo_nv4x @@ -0,0 +1,30 @@ +CONFIG_USE_OPTION_TABLE=y +CONFIG_TSEG_STAGE_CACHE=y +CONFIG_VENDOR_CLEVO=y +CONFIG_VBOOT=y +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Notebook" +CONFIG_BOARD_CLEVO_NV4X=y +CONFIG_PCIEXP_HOTPLUG_BUSES=42 +CONFIG_PCIEXP_HOTPLUG_MEM=0xc200000 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x1c00000 +CONFIG_USE_PM_ACPI_TIMER=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x30000 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="NV4XMB,ME,MZ" +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_SMMSTORE_V2=y +CONFIG_SMMSTORE_SIZE=0x40000 +# CONFIG_TPM_PPI is not set +CONFIG_CBFS_MCACHE_RW_PERCENTAGE=50 +CONFIG_VBOOT_KEYBLOCK_VERSION=1 +CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS=0x0 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_POST_IO_PORT=0x80 +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_CUSTOM=y +CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo" +CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS="-D PLATFORM_BOOT_TIMEOUT=2 -D BOOT_MENU_KEY=0x0011 -D SETUP_MENU_KEY=0x000C -D BOOTLOADER=COREBOOT -D PCIE_BASE=0xc0000000 -DPS2_KEYBOARD_ENABLE -D NETWORK_IPXE=TRUE -D SERIAL_TERMINAL=TRUE -D SECURE_BOOT_ENABLE=TRUE -D TPM_ENABLE=TRUE" diff --git a/src/ec/clevo/it5570/acpi/ec_ram.asl b/src/ec/clevo/it5570/acpi/ec_ram.asl index ce8cce0..dd7f0b6 100644 --- a/src/ec/clevo/it5570/acpi/ec_ram.asl +++ b/src/ec/clevo/it5570/acpi/ec_ram.asl @@ -290,12 +290,12 @@ OperationRegion (EC81, EmbeddedControl, Zero, 0xFF) Field (EC81, ByteAcc, Lock, Preserve) { - Offset (0xF8), - FCMD, 8, - FDAT, 8, - FBUF, 8, - FBF1, 8, - FBF2, 8, + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, FBF3, 8 }
diff --git a/src/mainboard/clevo/tgl-u/Kconfig b/src/mainboard/clevo/tgl-u/Kconfig new file mode 100644 index 0000000..cf422dd --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Kconfig @@ -0,0 +1,115 @@ +config BOARD_CLEVO_NV4X_BASE + bool "NV4x" + select BOARD_CLEVO_TGL_U_COMMON + select DRIVER_NVIDIA_OPTIMUS + +config BOARD_CLEVO_TGL_U_COMMON + def_bool n + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM + select NO_UART_ON_SUPERIO + select PCIEXP_HOTPLUG + select SOC_INTEL_TIGERLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select HAVE_SMI_HANDLER + select EC_CLEVO_IT5570 + select TPM_MEASURED_BOOT + +if BOARD_CLEVO_TGL_U_COMMON + +config MAINBOARD_DIR + string + default "clevo/tgl-u" + +config VARIANT_DIR + string + default "nv4x" if BOARD_CLEVO_NV4X_BASE + +config MAINBOARD_PART_NUMBER + string + default "nv4x" if BOARD_CLEVO_NV4X + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match stock firmware + +config MAX_CPUS + int + default 8 + +config PCIEXP_HOTPLUG + default y + +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c00000 # 448 MiB + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config DIMM_MAX + int + default 4 # Hack to make soc code work + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_ALWAYS_ENABLE_DISPLAY + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_A + default y + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +config UART_FOR_CONSOLE + int + default 2 + +config TPM_PIRQ + hex + default 0x1C # GPP_C14 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +# Getting the console output requires soldering the wires to the mainboard. +# Disable the serial output by default as it won't be commonly used and will +# only make the boot time longer. +config CONSOLE_SERIAL + default n + +endif # BOARD_CLEVO_TGL_U_COMMON diff --git a/src/mainboard/clevo/tgl-u/Kconfig.name b/src/mainboard/clevo/tgl-u/Kconfig.name new file mode 100644 index 0000000..5ea7dcd --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Kconfig.name @@ -0,0 +1,6 @@ +comment "Tiger Lake U" + +config BOARD_CLEVO_NV4X + bool "NV4x" + select BOARD_CLEVO_NV4X_BASE + diff --git a/src/mainboard/clevo/tgl-u/Makefile.inc b/src/mainboard/clevo/tgl-u/Makefile.inc new file mode 100644 index 0000000..f7cc796 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/Makefile.inc @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += memory.c +romstage-y += romstage.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/tgl-u/acpi/mainboard.asl b/src/mainboard/clevo/tgl-u/acpi/mainboard.asl new file mode 100644 index 0000000..5e74220 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/mainboard.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SLPB 0x6B // PME_STS +#define EC_GPE_LID 0x6B // PME_STS +#define EC_GPE_SCI 0x6E // ESPI_SCI +#define EC_GPE_PWRB 0x43 // GPD9 Power Button +#define EC_GPE_RTC 0x72 // RTC Alarm Status +// echo '_SB.SLPB._PRW' | sudo tee /proc/acpi/call; sudo cat /proc/acpi/call +// echo '_SB.PC00.LPCB.EC._GPE' | sudo tee /proc/acpi/call; sudo cat /proc/acpi/call + +Scope (_SB) { + #include "sleep.asl" + + #include <ec/clevo/it5570/acpi/ac.asl> + #include <ec/clevo/it5570/acpi/battery.asl> + #include <ec/clevo/it5570/acpi/buttons.asl> + #include <ec/clevo/it5570/acpi/lid.asl> + + Scope (PCI0.LPCB) { + #include <ec/clevo/it5570/acpi/ec.asl> + } +} + +Scope (_GPE) { + #include <ec/clevo/it5570/acpi/gpe.asl> +} diff --git a/src/mainboard/clevo/tgl-u/acpi/sleep.asl b/src/mainboard/clevo/tgl-u/acpi/sleep.asl new file mode 100644 index 0000000..bfcb487 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/sleep.asl @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/gpio.h> + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + _SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + _SB.PCI0.LPCB.EC0.PTS (Arg0) + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) + _SB.PCI0.LPCB.EC0.WAK (Arg0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from _SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + } +} + +/* + * Display On/Off Notifications + * Called from _SB.PEPD._DSM + */ +Method (MDSX, 1, Serialized) +{ + If (Arg0 == 1) { + /* Display On */ + _SB.PCI0.LPCB.EC0.MSFG = Zero + } Else { + /* Display Off */ + If ((_SB.PCI0.LPCB.EC0.S5FG != One)) + { + _SB.PCI0.LPCB.EC0.MSFG = One + } + } +} diff --git a/src/mainboard/clevo/tgl-u/board.fmd b/src/mainboard/clevo/tgl-u/board.fmd new file mode 100644 index 0000000..c47e6a4 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/board.fmd @@ -0,0 +1,13 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL 5M { + SI_DESC 4K + SI_ME + } + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + FMAP 4K + COREBOOT(CBFS) +} diff --git a/src/mainboard/clevo/tgl-u/board_info.txt b/src/mainboard/clevo/tgl-u/board_info.txt new file mode 100644 index 0000000..5822307 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Clevo +Category: laptop +Release year: 2021 +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/tgl-u/bootblock.c b/src/mainboard/clevo/tgl-u/bootblock.c new file mode 100644 index 0000000..a434521 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/bootblock.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <console/console.h> +#include <delay.h> +#include <gpio.h> + +#define DGPU_RST_N GPP_U4 +#define DGPU_PWR_EN GPP_U5 + +static void dgpu_power_enable(int onoff) { + printk(BIOS_DEBUG, "nvidia: DGPU power %d\n", onoff); + if (onoff) { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + mdelay(4); + gpio_set(DGPU_RST_N, 1); + } else { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 0); + } + mdelay(50); +} + +void bootblock_mainboard_early_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); + dgpu_power_enable(1); +} diff --git a/src/mainboard/clevo/tgl-u/cmos.default b/src/mainboard/clevo/tgl-u/cmos.default new file mode 100644 index 0000000..39b95be --- /dev/null +++ b/src/mainboard/clevo/tgl-u/cmos.default @@ -0,0 +1,2 @@ +boot_option=Fallback +preserve_smmstore=0 diff --git a/src/mainboard/clevo/tgl-u/cmos.layout b/src/mainboard/clevo/tgl-u/cmos.layout new file mode 100644 index 0000000..942a6b3 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/cmos.layout @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +#395 4 e 3 debug_level +408 1 h 1 preserve_smmstore +984 16 h 0 check_sum + +enumerations + +1 0 Disable +1 1 Enable + +2 0 Fallback +2 1 Normal + +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/clevo/tgl-u/dsdt.asl b/src/mainboard/clevo/tgl-u/dsdt.asl new file mode 100644 index 0000000..6e5dd9e --- /dev/null +++ b/src/mainboard/clevo/tgl-u/dsdt.asl @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/tigerlake/acpi/southbridge.asl> + #include <soc/intel/tigerlake/acpi/tcss.asl> + #include <soc/intel/common/block/acpi/acpi/ipu.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + + Scope (_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + // Mainboard specific + #include <acpi/mainboard.asl> +} diff --git a/src/mainboard/clevo/tgl-u/mainboard.c b/src/mainboard/clevo/tgl-u/mainboard.c new file mode 100644 index 0000000..24167c7 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/mainboard.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <device/device.h> +#include <intelblocks/lpc_lib.h> +#include <soc/gpio.h> +#include <smbios.h> +#include <string.h> + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + /* Configure MMIO window before FSP-S locks the DMI registers */ + lpc_open_mmio_window(CONFIG_EC_CLEVO_IT5570_RAM_BASE, 0x10000); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/clevo/tgl-u/memory.c b/src/mainboard/clevo/tgl-u/memory.c new file mode 100644 index 0000000..e0f01a9 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/memory.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/romstage.h> +#include <baseboard/variants.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + variant_configure_fspm(mupd); +} diff --git a/src/mainboard/clevo/tgl-u/romstage.c b/src/mainboard/clevo/tgl-u/romstage.c new file mode 100644 index 0000000..be7494e --- /dev/null +++ b/src/mainboard/clevo/tgl-u/romstage.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> +#include <baseboard/variants.h> + +static const struct mb_cfg variant_mem_config = { + .type = MEM_TYPE_DDR4, + .ect = false, /* Early Command Training */ + .ddr4_config = { + .dq_pins_interleaved = false, + } +}; + +static const struct mem_spd variant_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, +}; + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + const struct mb_cfg *mem_config = &variant_mem_config; + const struct mem_spd *spd_info = &variant_spd_info; + const bool half_populated = false; + + memcfg_init(&memupd->FspmConfig, mem_config, spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + memupd->FspmConfig.VtdDisable = !vtd; + + const uint8_t ht = get_uint_option("hyper_threading", + memupd->FspmConfig.HyperThreading); + memupd->FspmConfig.HyperThreading = ht; +} diff --git a/src/mainboard/clevo/tgl-u/smihandler.c b/src/mainboard/clevo/tgl-u/smihandler.c new file mode 100644 index 0000000..26d6438 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/smihandler.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/clevo/it5570/ec.h> +#include <intelblocks/smihandler.h> + +void mainboard_smi_espi_handler(void) +{ + printk(BIOS_DEBUG, "Mainboard SMI eSPI handler\n"); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + printk(BIOS_DEBUG, "Mainboard SMI sleep handler: %02x\n", slp_typ); +} + +int mainboard_smi_apmc(u8 apmc) +{ + printk(BIOS_DEBUG, "Mainboard SMI APMC handler: %02x\n", apmc); + clevo_it5570_ec_smi_apmc(apmc); + return 0; +} diff --git a/src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..4281387 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb @@ -0,0 +1,129 @@ +chip soc/intel/tigerlake + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Disable DPTF + register "dptf_enable" = "0" + + # Enable External Bypass + register "external_bypass" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable s0ix, required for TGL-U + register "s0ix_enable" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + # Enable C6 DRAM + register "enable_c6dram" = "1" + + # System Agent dynamic frequency support + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + +# FIVR configuration + # Read EXT_RAIL_CONFIG to determine bitmaps + # sudo devmem2 0xfe0011b8 + # 0x0 + # Read EXT_V1P05_VR_CONFIG + # sudo devmem2 0xfe0011c0 + # 0x1a42000 + # Read EXT_VNN_VR_CONFIG0 + # sudo devmem2 0xfe0011c4 + # 0x1a42000 + # TODO: v1p05 voltage and vnn icc max? + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = 0, + .vnn_enable_bitmap = 0, + .v1p05_supported_voltage_bitmap = 0, + .vnn_supported_voltage_bitmap = 0, + .v1p05_icc_max_ma = 500, + .vnn_sx_voltage_mv = 1050, + }" + + # LPM states + register "LpmStateDisableMask" = " + LPM_S0i2_1 | + LPM_S0i2_2 | + LPM_S0i3_1 | + LPM_S0i3_2 | + LPM_S0i3_3 | + LPM_S0i3_4 + " + + # Enable CNVi BT + register "CnviBtCore" = "true" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + #From CPU EDS(575683) + device ref system_agent on end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + # ACPI brightness control + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref shared_ram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c1 on + # USB-PD + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref heci1 on end + device ref p2sb on end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # TBT Type-C + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref pch_espi on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..b61276c --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h b/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..20ce364 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ + +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +void variant_configure_fspm(FSPM_UPD *memupd); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc b/src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc new file mode 100644 index 0000000..2438407 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt b/src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt new file mode 100644 index 0000000..8db7db3 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/board_info.txt @@ -0,0 +1 @@ +Board name: NV4x diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt b/src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt new file mode 100644 index 0000000..369d07d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/data.vbt Binary files differ diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c b/src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c new file mode 100644 index 0000000..8d2f24c --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/gpio.c @@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B15, 1, DEEP), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* ------- GPIO Group GPP_T (TGL UP3 only) ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D13, 0, DEEP), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_U (TGL UP3 only) ------- */ + //PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */ + //PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + PAD_CFG_NF(GPD2, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPD7, 1, RSMRST), + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + PAD_CFG_GPI_TRIG_OWN(GPD9, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPD11, UP_20K, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_NC(GPP_C5, NONE), + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, DEEP), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPO(GPP_F7, 1, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_CFG_GPO(GPP_F9, 1, DEEP), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_GPO(GPP_E1, 0, PLTRST), + PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_E17, NONE), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */ + PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP), /* DGPU_RST#_PCH */ + PAD_CFG_TERM_GPO(GPP_U5, 0, NONE, DEEP), /* DGPU_PWR_EN */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c new file mode 100644 index 0000000..1979c95 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15584019, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15584018), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Tigerlake HDMI */ + 0x80862812, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb b/src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb new file mode 100644 index 0000000..02c5511 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv4x/overridetree.cb @@ -0,0 +1,234 @@ +chip soc/intel/tigerlake +# CPU (soc/intel/tigerlake/cpu.c) + # Power limits + # TODO: Check if this is correct + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + # Thermal + register "tcc_offset" = "13" + +# PM Util (soc/intel/tigerlake/pmutil.c) + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_C" + register "pmc_gpe0_dw1" = "PMC_GPP_E" + register "pmc_gpe0_dw2" = "PMC_GPD" + +# Actual device tree + device domain 0 on + subsystemid 0x1558 0x4018 inherit + + device ref peg on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD1"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end + + # Disable Optane hybrid storage mode + register "HybridStorageMode" = "0" + end + device ref tbt_pcie_rp0 on end # TBT Type-C + device ref north_xhci on # TBT Type-C + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # TBT Type-C + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB-A port1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB-A port3 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Finger + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TBT USB-C + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # CCD + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C port2 (right port, lane 0) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C port4 (right port, lane 1) + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 4"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c2 on + # Pantone ROM + register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" + end + device ref pcie_rp5 on + # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[2]" = "4" + register "PcieClkSrcClkReq[2]" = "2" + chip drivers/gfx/nvidia/optimus + register "desc" = ""DGPU"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH + register "enable_delay_ms" = "16" + register "enable_off_delay_ms" = "4" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "4" + register "srcclk_pin" = "2" # PEG_CLKREQ# + register "ec_notify_method" = ""\_SB.PCI0.LPCB.EC0.DGPM"" + device generic 0 on end + end + end + device ref pcie_rp9 on + # PCIe root port #9 x1, Clock 3 (CARD) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device ref pcie_rp10 on + # PCIe root port #10 x1, Clock 4 (GLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + register "PcieClkSrcUsage[4]" = "9" + register "PcieClkSrcClkReq[4]" = "4" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST + register "srcclk_pin" = "4" # LAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp11 on + # PCIe root port #11 x1, Clock 1 (WLAN) + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_23" # GPP_C23 + device pci 00.0 on end + end + end + device ref pch_espi on + chip ec/clevo/it5570 + device pnp 0c09.0 on end + register "fan_mode" = "FAN_MODE_CUSTOM" + register "fans[0].curve.temperature" = "{ 40, 60, 70, 80 }" + register "fans[0].curve.speed" = "{ 16, 25, 50, 100 }" + register "fans[1].curve.temperature" = "{ 40, 60, 70, 80 }" + register "fans[1].curve.speed" = "{ 16, 25, 50, 100 }" + end + end + device ref hda on + subsystemid 0x1558 0x4019 + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + end + end +end + diff --git a/src/mainboard/clevo/tgl-u/vboot-rwa.fmd b/src/mainboard/clevo/tgl-u/vboot-rwa.fmd new file mode 100644 index 0000000..5385db3 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/vboot-rwa.fmd @@ -0,0 +1,38 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL 5M { + SI_DESC 4K + SI_ME + } + + RW_MISC 400K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_SHARED 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + } + + RW_SECTION_A { + VBLOCK_A 0x2000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + + CONSOLE 0x20000 + + # align this with a WP region? + WP_RO 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } +}