[coreboot-gerrit] [S] Change in coreboot[main]: mtlrvp: add SI_EC region in flash map

[Deepti Deshatty (Code Review)]

Attention is currently required from: Deepti Deshatty.

Hello Deepti Deshatty,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/coreboot/+/79209?usp=email

to review the following change.

Change subject: mtlrvp: add SI_EC region in flash map
......................................................................

mtlrvp: add SI_EC region in flash map

MTLRVP booted with microchip EC1723 which do not have an
internal flash memory similar to the windows RVP designs.
Using MEC1723 for chrome helps in RVP BOM convergence.

EC, AP shares the same external SPI flash. EC ROM will
download the EC firmware from external SPI to internal SRAM
for execution.
This patch adds SI_EC region similar to windows.

Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84
Signed-off-by: Deepti Deshatty 
---
M src/mainboard/intel/mtlrvp/Kconfig
M src/mainboard/intel/mtlrvp/chromeos.fmd
2 files changed, 12 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/1

diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index f225aa5..a4e5e1a 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -99,7 +99,8 @@
 choice
    prompt "ON BOARD EC"
    default MTL_INTEL_EC if BOARD_INTEL_MTLRVP_P
-	default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP
+	default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC
+	default MTL_CHROME_EC_SHARED_SPI if BOARD_INTEL_MTLRVP_P_MCHP
    help
      This option allows you to select the on board EC to use.
      Select whether the board has Intel EC or/and Chrome EC
@@ -111,6 +112,14 @@
    select EC_GOOGLE_CHROMEEC_ESPI
    select EC_GOOGLE_CHROMEEC_BOARDID

+config MTL_CHROME_EC_SHARED_SPI
+	bool "Chrome EC with external Shared SPI flash"
+	select EC_ACPI
+	select EC_GOOGLE_CHROMEEC
+	select EC_GOOGLE_CHROMEEC_ESPI
+	select EC_GOOGLE_CHROMEEC_BOARDID
+	select MAINBOARD_USES_IFD_EC_REGION
+
 config MTL_INTEL_EC
    bool "Intel EC"
    select EC_ACPI
@@ -118,7 +127,7 @@

config VBOOT
    select VBOOT_LID_SWITCH
-	select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC
+	select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC || MTL_CHROME_EC_SHARED_SPI

config UART_FOR_CONSOLE
    int
diff --git a/src/mainboard/intel/mtlrvp/chromeos.fmd b/src/mainboard/intel/mtlrvp/chromeos.fmd
index a5bc538..d49ac0c7 100644
--- a/src/mainboard/intel/mtlrvp/chromeos.fmd
+++ b/src/mainboard/intel/mtlrvp/chromeos.fmd
@@ -1,6 +1,7 @@
 FLASH 32M {
    SI_ALL 9M {
    	SI_DESC 16K
+		SI_EC 512K
    	SI_ME
    }
    SI_BIOS 23M {