Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )
Change subject: soc/intel/tigerlake: Support to initialize Memory ......................................................................
Patch Set 12:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39847/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39847/12//COMMIT_MSG@7 PS12, Line 7: soc/intel/tigerlake: Support to initialize Memory Add support to initialize memory
https://review.coreboot.org/c/coreboot/+/39847/12//COMMIT_MSG@10 PS12, Line 10: Added Add
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/in... File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/in... PS12, Line 104: * DQS CPU<>DRAM map. Each array entry represents a : * mapping of a dq bit on the CPU to the bit it's connected to on : * the memory part. The array index represents the dqs bit number : * on the memory part, and the values in the array represent which : * pin on the CPU that DRAM pin connects to. Please re-flow for 80 or 96 characters per line.
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/me... File src/soc/intel/tigerlake/meminit_tgl.c:
https://review.coreboot.org/c/coreboot/+/39847/12/src/soc/intel/tigerlake/me... PS12, Line 337: */ Please format the comment correctly by aligning the asterisks and adding a dot after an asterisk.
https://doc.coreboot.org/coding_style.html#commenting