Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44711 )
Change subject: soc/mediatek/mt8192: Add DDR mode register init ......................................................................
Patch Set 43:
(10 comments)
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/Ma... File src/soc/mediatek/mt8192/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/Ma... PS43, Line 28: romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c Line too long. Please split to 2 lines.
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 124: mr_value->mr03[FSP_1] = 0x30 | 0x4; : mr_value->mr03[FSP_1] |= 0x2; mr_value->mr03[FSP_1] = 0x30 | 0x4 | 0x2;
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 3807: size_t int
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 3817: SPCMDRESP3_ZQC_SWTRIG_RESPONSE Align with &ch[chn]
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 3818: fail failed
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 3826: SPCMDRESP3_ZQLAT_SWTRIG_RESPONSE Align with &ch[chn]
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 3827: fail failed
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 3833: size_t int
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 3838: u8 chn Align with 'const struct ddr_cali'
https://review.coreboot.org/c/coreboot/+/44711/43/src/soc/mediatek/mt8192/dr... PS43, Line 3863: if frequency is same to last If frequency is the same as before