[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Support to initialize Memory

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39847 )

Change subject: soc/intel/tigerlake: Support to initialize Memory
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Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39847/5/src/soc/intel/tigerlake/mem... 
File src/soc/intel/tigerlake/meminit_tgl.c:

https://review.coreboot.org/c/coreboot/+/39847/5/src/soc/intel/tigerlake/mem... 
PS5, Line 89: 	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0);
            : 	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1);
            : 	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2);
            : 	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3);
            : 	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4);
            : 	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5);
            : 	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6);
            : 	MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7
> Could not do it with macro defined

I don't think this is completely correct. DDR4 only supports 2 channels.

https://review.coreboot.org/c/coreboot/+/39847/5/src/soc/intel/tigerlake/mem... 
PS5, Line 179: meminit_ddr4x_sodimm
I think we can reorganize this file slightly different to allow easier sharing and also enable support for different configurations. Let me see if I can rearrange the LPDDR4x code and you can rebase on top of it.