[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/ramstage: Fix compilation issue

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46053 )

Change subject: soc/intel/alderlake/ramstage: Fix compilation issue
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Patch Set 1:
> Patch Set 1: Code-Review+2
> > Patch Set 1:
> >
> > HI Angel, Tim,
> >
> > Please consider my apology that I've missed rebasing ADL ramstage CL based on common code CLs hence it results into compilation issue.
> >
> > Submitting this now. As we have mainboard code ready, hopefully won't rerepeat such mistake for ADL SoC.
> >
> > Thanks,
> > Subrata
>
> No problem. See, having the code build-tested from the very start is very useful 😄

agree Angel. i had that plan from beginning but somehow this timeline forced me to go with SOC first model but i will make sure from next SoC onwards we are going with incremental SoC + MB CL from day 1.