Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10591
-gerrit
commit f77ff1f78e621fb6e200f9bb3c4e8f5986610b22 Author: Stefan Reinauer stefan.reinauer@coreboot.org Date: Thu Jun 18 22:01:07 2015 -0700
oprom: Fix for 64bit
Change-Id: If4c1ab5ae33a64be3e7b14150d410edd291ee4ed Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/device/oprom/realmode/x86.c | 2 +- src/device/pci_rom.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 485d1a4..14bcbc0 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -188,7 +188,7 @@ static void setup_realmode_idt(void) for (i = 0; i < 256; i++) { idts[i].cs = 0; idts[i].offset = 0x1000 + (i * __idt_handler_size); - write_idt_stub((void *)((u32 )idts[i].offset), i); + write_idt_stub((void *)((uintptr_t)idts[i].offset), i); }
/* Many option ROMs use the hard coded interrupt entry points in the diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 26cd6cf..80b2a51 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -57,7 +57,7 @@ struct rom_header *pci_rom_probe(struct device *dev) printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n", dev_path(dev), rom_header); } else { - u32 rom_address; + uintptr_t rom_address;
rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);