[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Allow fine grained control of S0iX states

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44355 )

Change subject: soc/intel/tigerlake: Allow fine grained control of S0iX states
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Patch Set 5:
> Patch Set 5: Code-Review-1
>
> According to my prior comment, I do not believe this CL is necessary for my feature.  I am delaying fully abandoning it, though, until I am sure.

In my opinion, it is better to keep all the FSP_S UPD updates within the SoC code and only touch soc_config from mainboard. Thus, let's add LpmStateDisableMask as you have in this CL. (In the follow-up CL, you will have to perform the config setting in a different place than it is currently done - I will post a comment there).