Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36093 )
Change subject: mb/lenovo/x200: Add ThinkPad X301 as a variant ......................................................................
mb/lenovo/x200: Add ThinkPad X301 as a variant
It is similar to X200s, with U-series CPU, slightly different gpio setup, and no docking support, thus no superio chip in dock.
Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios.
Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE persmule@hardenedlinux.org --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/x301.md A Documentation/mainboard/lenovo/x301_kb_removed.jpg M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Kconfig.name M src/mainboard/lenovo/x200/Makefile.inc M src/mainboard/lenovo/x200/board_info.txt M src/mainboard/lenovo/x200/devicetree.cb A src/mainboard/lenovo/x200/variants/x200/board_info.txt R src/mainboard/lenovo/x200/variants/x200/dock.c R src/mainboard/lenovo/x200/variants/x200/gpio.c A src/mainboard/lenovo/x200/variants/x200/overridetree.cb A src/mainboard/lenovo/x200/variants/x301/board_info.txt A src/mainboard/lenovo/x200/variants/x301/dock.c A src/mainboard/lenovo/x200/variants/x301/gpio.c A src/mainboard/lenovo/x200/variants/x301/overridetree.cb M src/southbridge/intel/i82801ix/nvs.h 17 files changed, 294 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/36093/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c9204f6..2aa2763 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -72,6 +72,10 @@
- [T410](lenovo/t410.md)
+### GM45 series + +- [X301](lenovo/x301.md) + ### Sandy Bridge series
- [T420](lenovo/t420.md) diff --git a/Documentation/mainboard/lenovo/x301.md b/Documentation/mainboard/lenovo/x301.md new file mode 100644 index 0000000..5c6f771 --- /dev/null +++ b/Documentation/mainboard/lenovo/x301.md @@ -0,0 +1,27 @@ +# Lenovo X301 + +## Disassembly Instructions + +You must remove the following parts to access the SPI flash: + + + +* Battery pack +* Keyboard + +Its [Hardware Maintenance Manual](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/43y9441.pdf) could be used as a guidance of disassembly. + +The WSON-8 flash chip (surrounded with red circle in the photo above, +already replaced with a SOIC-8 one) sits under a piece of insulating +tape. If solders between the chip and soldering pads fortunately +overflows beside the chip as tiny tin balls attached to soldering pads, +it will be possible to use a pomona 5250 clip to hold the chip, with +its metal tips just attached to tin balls, thus connecting the chip to +the programmer. Otherwise, it may be recommended to replace it with a +SOIC-8 one. (as what is done in the photo) + +```eval_rst +:doc:`../../flash_tutorial/ext_power` +``` + +[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md diff --git a/Documentation/mainboard/lenovo/x301_kb_removed.jpg b/Documentation/mainboard/lenovo/x301_kb_removed.jpg new file mode 100644 index 0000000..b9f8090 --- /dev/null +++ b/Documentation/mainboard/lenovo/x301_kb_removed.jpg Binary files differ diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 7b905bc..fab8a88 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X200 +if BOARD_LENOVO_X200 || BOARD_LENOVO_X301
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,9 +28,19 @@ string default lenovo/x200
+config VARIANT_DIR + string + default "x200" if BOARD_LENOVO_X200 + default "x301" if BOARD_LENOVO_X301 + config MAINBOARD_PART_NUMBER string - default "ThinkPad X200" + default "ThinkPad X200" if BOARD_LENOVO_X200 + default "ThinkPad X301" if BOARD_LENOVO_X301 + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config USBDEBUG_HCD_INDEX int @@ -44,4 +54,4 @@ hex default 0x200000
-endif # BOARD_LENOVO_X200 +endif # BOARD_LENOVO_X200 || BOARD_LENOVO_X301 diff --git a/src/mainboard/lenovo/x200/Kconfig.name b/src/mainboard/lenovo/x200/Kconfig.name index 8e1dd43..54c7961 100644 --- a/src/mainboard/lenovo/x200/Kconfig.name +++ b/src/mainboard/lenovo/x200/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_LENOVO_X200 - bool "ThinkPad X200 / X200t" + bool "ThinkPad X200 / X200s / X200t" + +config BOARD_LENOVO_X301 + bool "ThinkPad X301" diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index ffd7cf2..f6c2c0c 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -13,10 +13,10 @@ ## GNU General Public License for more details. ##
-ramstage-y += dock.c +ramstage-y += variants/$(VARIANT_DIR)/dock.c ramstage-y += cstates.c ramstage-y += blc.c -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x200/board_info.txt b/src/mainboard/lenovo/x200/board_info.txt index c9cc003..6f27955 100644 --- a/src/mainboard/lenovo/x200/board_info.txt +++ b/src/mainboard/lenovo/x200/board_info.txt @@ -1,5 +1,6 @@ Category: laptop -ROM package: SOIC-16 or SOIC-8 +Board name: ThinkPad X200 baseboard +ROM package: SOIC-16 or SOIC-8 or WSON8 ROM protocol: SPI ROM socketed: n Flashrom support: n diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 4efcc25..fdd69ec 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -73,12 +73,6 @@ # Set thermal throttling to 75%. register "throttle_duty" = "THTL_75_0"
- # Enable PCIe ports 1,2,4 as slots (Mini * PCIe). - register "pcie_slot_implemented" = "0xb" - # Set power limits to 10 * 10^0 watts. - # Maybe we should set less for Mini PCIe. - register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "gen1_dec" = "0x007c1601" register "gen2_dec" = "0x000c15e1" register "gen3_dec" = "0x001c1681" @@ -114,10 +108,7 @@ device pci 1c.2 on subsystemid 0x17aa 0x20f3 # UWB end # PCIe Port #3 - device pci 1c.3 on - subsystemid 0x17aa 0x20f3 # Expresscard - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 + # PCIe Port #4 is configured in override tree. device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 device pci 1d.0 on # UHCI @@ -154,7 +145,6 @@ device pnp ff.1 on # dummy end register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" end
chip ec/lenovo/h8 @@ -192,22 +182,6 @@ register "bdc_gpio_num" = "7" register "bdc_gpio_lvl" = "0" end - - chip superio/nsc/pc87382 - device pnp 164e.3 on # Digitizer - io 0x60 = 0x200 - irq 0x29 = 0xb0 - irq 0x70 = 0x5 - irq 0xf0 = 0x82 - end - # IR, not connected - device pnp 164e.2 off end - # GPIO, not connected - device pnp 164e.7 off end - # DLPC, not connected - device pnp 164e.19 off end - end - end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 diff --git a/src/mainboard/lenovo/x200/variants/x200/board_info.txt b/src/mainboard/lenovo/x200/variants/x200/board_info.txt new file mode 100644 index 0000000..c9cc003 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x200/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-16 or SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2008 diff --git a/src/mainboard/lenovo/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c similarity index 96% rename from src/mainboard/lenovo/x200/dock.c rename to src/mainboard/lenovo/x200/variants/x200/dock.c index d5f774b..019d079 100644 --- a/src/mainboard/lenovo/x200/dock.c +++ b/src/mainboard/lenovo/x200/variants/x200/dock.c @@ -26,11 +26,11 @@ #include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h>
-#include "dock.h" +#include "../../dock.h"
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-void h8_mainboard_init_dock (void) +void h8_mainboard_init_dock(void) { if (dock_present()) { printk(BIOS_DEBUG, "dock is connected\n"); diff --git a/src/mainboard/lenovo/x200/gpio.c b/src/mainboard/lenovo/x200/variants/x200/gpio.c similarity index 100% rename from src/mainboard/lenovo/x200/gpio.c rename to src/mainboard/lenovo/x200/variants/x200/gpio.c diff --git a/src/mainboard/lenovo/x200/variants/x200/overridetree.cb b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb new file mode 100644 index 0000000..dd08f1f --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x200/overridetree.cb @@ -0,0 +1,38 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + # Enable PCIe ports 1,2,3,4 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0xf" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 10, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }" + # Enable hotplug on PCIe port 4 (Express Card) + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 1c.3 on + subsystemid 0x17aa 0x20f3 # Expresscard + smbios_slot_desc "7" "3" "ExpressCard Slot" "8" + end # PCIe Port #4 + + device pci 1f.0 on # LPC bridge + chip ec/lenovo/pmh7 + register "dock_event_enable" = "0x01" + end + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end + end + end + end +end diff --git a/src/mainboard/lenovo/x200/variants/x301/board_info.txt b/src/mainboard/lenovo/x200/variants/x301/board_info.txt new file mode 100644 index 0000000..6ee5df0 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2008 diff --git a/src/mainboard/lenovo/x200/variants/x301/dock.c b/src/mainboard/lenovo/x200/variants/x301/dock.c new file mode 100644 index 0000000..a180d64 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/dock.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle svens@stackframe.org + * Copyright (C) 2013 Vladimir Serbinenko phcoder@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <ec/lenovo/h8/h8.h> +#include "../../dock.h" + +void h8_mainboard_init_dock(void) +{ +} + +void dock_connect(void) +{ +} + +void dock_disconnect(void) +{ +} + +int dock_present(void) +{ + return 0; +} diff --git a/src/mainboard/lenovo/x200/variants/x301/gpio.c b/src/mainboard/lenovo/x200/variants/x301/gpio.c new file mode 100644 index 0000000..01421a9 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/gpio.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio9 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/lenovo/x200/variants/x301/overridetree.cb b/src/mainboard/lenovo/x200/variants/x301/overridetree.cb new file mode 100644 index 0000000..fafe5e9 --- /dev/null +++ b/src/mainboard/lenovo/x200/variants/x301/overridetree.cb @@ -0,0 +1,14 @@ +chip northbridge/intel/gm45 + device domain 0 on + chip southbridge/intel/i82801ix + # Enable PCIe ports 1,2,3 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0x7" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }" + # x301 has no Express Card slot. + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + device pci 1c.3 off end # PCIe Port #4 + end + end +end diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index 04e62db..607c225 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -13,6 +13,10 @@ * GNU General Public License for more details. */
+#ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H +#define SOUTHBRIDGE_INTEL_I82801IX_NVS_H +#include <stdint.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -133,3 +137,5 @@ } __packed global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs); + +#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H */