[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/cse: Implement HECI notify

[Subrata Banik (Code Review)]

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60405 )

Change subject: soc/intel/common/cse: Implement HECI notify
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Patch Set 8:

(1 comment)

File src/soc/intel/common/block/cse/cse_eop.c:

https://review.coreboot.org/c/coreboot/+/60405/comment/697cc181_8e8bea8c 
PS7, Line 279: HeciEnabled
> Yes I have been on vacation, good guess 😄

:) sorry to pull you in from your vacation Tim
> I think I like where you're going here guys:
> 0) Drop HeciEnabled
> Always keep the HECI devices (at least HECI1) to perform all of the CSE operations, instead of using BOOT_STATE entries
> A Kconfig to decide whether or not to "function disable" the CSE/HECI devices before booting the payload.
> a) The means of doing this (via HECI_DISABLE_USING_SMM for example) is chipset-specific and irrelevant to the point at hand.
>
> This means coreboot can handle all of the required CSE operations, but the user can decide to disable CSE before payload if desired.

Thanks Angel and Tim for your suggestion. I will pick this up tomorrow and rebase this CL.