[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39980 )

Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
......................................................................

soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default

There are boards that do not need a specific domain_vr_config because
the defaults provided by the soc code are sufficient. Currently, this
means that these boards can't benefit from lower power states (PSI 3
and 4) because the settings default to being disabled since at the time
the defaults have been defined (2015) there were bugs in FSP in this
regard.

Set the default values of psiXenable to 1 for boards that do not have a
domain_vr_config setting in their devicetree, just like Cannon Lake
does.

Boards that have a domain_vr_config and set their specific settings are
not affected at all. Currently, there are only three boards that have
no domain_vr_config:

- supermicro/x11-lga1151-series
  These boards have a MPS MP2955 which we can assume support for PS3
  (the MP2965 and MP2935 support it, too).
  S-series CPUs with a 1151 socket do not have C9/C10 but only C8 and
  since only C10 makes use of PS4, those CPUs won't ever request PS4.
  That means we do not need to disable it explicitly for these boards.

- 51nb/x210:
  Needs testing and/or VR datasheet check for PS3/PS4 support

Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39980
Reviewed-by: Matt DeVillier 
Reviewed-by: Benjamin Doron 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/vr_config.c
1 file changed, 9 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Benjamin Doron: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 98d2513..57c55ec 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -21,15 +21,15 @@
 #include <console/console.h>
 #include <intelblocks/cpulib.h>

-/* Default values for domain configuration. PSI3 and PSI4 are disabled. */
+/* Default values for domain configuration. */
 static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
    [VR_SYSTEM_AGENT] = {
    	.vr_config_enable = 1,
    	.psi1threshold = VR_CFG_AMP(20),
    	.psi2threshold = VR_CFG_AMP(4),
    	.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 0,
-		.psi4enable = 0,
+		.psi3enable = 1,
+		.psi4enable = 1,
    	.imon_slope = 0,
    	.imon_offset = 0,
    	.icc_max = 0,
@@ -40,8 +40,8 @@
    	.psi1threshold = VR_CFG_AMP(20),
    	.psi2threshold = VR_CFG_AMP(5),
    	.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 0,
-		.psi4enable = 0,
+		.psi3enable = 1,
+		.psi4enable = 1,
    	.imon_slope = 0,
    	.imon_offset = 0,
    	.icc_max = 0,
@@ -52,8 +52,8 @@
    	.psi1threshold = VR_CFG_AMP(20),
    	.psi2threshold = VR_CFG_AMP(5),
    	.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 0,
-		.psi4enable = 0,
+		.psi3enable = 1,
+		.psi4enable = 1,
    	.imon_slope = 0,
    	.imon_offset = 0,
    	.icc_max = 0,
@@ -64,8 +64,8 @@
    	.psi1threshold = VR_CFG_AMP(20),
    	.psi2threshold = VR_CFG_AMP(5),
    	.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 0,
-		.psi4enable = 0,
+		.psi3enable = 1,
+		.psi4enable = 1,
    	.imon_slope = 0,
    	.imon_offset = 0,
    	.icc_max = 0,