Attention is currently required from: Werner Zeh.
Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74938 )
Change subject: mb/siemens/mc_ehl5: Adjust the settings for the PCIe root ports ......................................................................
mb/siemens/mc_ehl5: Adjust the settings for the PCIe root ports
This mainboard has three connected PCIe devices. This patch enables and configures the required root ports.
Change-Id: I8f7ef1ac35d78a6d5863ffbbc367addd820f4004 Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb 1 file changed, 25 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/74938/1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index 31002c0..76be791 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -41,13 +41,15 @@
# PCIe root ports related UPDs register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[4]" = "1"
- register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" - register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" - register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"
register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED" @@ -58,9 +60,13 @@
# Disable all L1 substates for PCIe root ports register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
# Disable LTR for all PCIe root ports register "PcieRpLtrDisable[1]" = "true" + register "PcieRpLtrDisable[2]" = "true" + register "PcieRpLtrDisable[4]" = "true"
# Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "0" @@ -181,6 +187,8 @@ device pci 1a.1 on end # SD
device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.2 on end # RP3 (pcie0 single VC) + device pci 1c.4 on end # RP5 (pcie1 multi VC)
device pci 1d.0 off end # Intel PSE IPC (local host to PSE) device pci 1d.1 on # Intel PSE Time-Sensitive Networking GbE 0