Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74807 )
Change subject: soc/amd: Reserve PCIe MMCONF in ACPI ......................................................................
soc/amd: Reserve PCIe MMCONF in ACPI
Linux complains about this: "[Firmware Info]: PCI: MMCONFIG at [mem 0cf8000000-0xfbffffff] not reserved in ACPI motherboard resources"
Signed-off-by: Arthur Heymans arthur@aheymans.xyz Change-Id: I33e8d7f5057099ffa92853e8df52bb2aee968957 --- M src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/glinda/acpi/pci0.asl M src/soc/amd/mendocino/acpi/pci0.asl M src/soc/amd/phoenix/acpi/pci0.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 6 files changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/74807/1
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl index 93bfb1f..75c90ac 100644 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ b/src/soc/amd/cezanne/acpi/pci0.asl @@ -58,6 +58,8 @@
/* memory space for PCI BARs below 4GB */ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* MMCONF */ + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) })
Method(_CRS, 0) { diff --git a/src/soc/amd/glinda/acpi/pci0.asl b/src/soc/amd/glinda/acpi/pci0.asl index 2f7e0ba..6b6c00e 100644 --- a/src/soc/amd/glinda/acpi/pci0.asl +++ b/src/soc/amd/glinda/acpi/pci0.asl @@ -60,6 +60,8 @@
/* memory space for PCI BARs below 4GB */ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* MMCONF */ + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) })
Method(_CRS, 0) { diff --git a/src/soc/amd/mendocino/acpi/pci0.asl b/src/soc/amd/mendocino/acpi/pci0.asl index 5bf2f3e..4f674a5 100644 --- a/src/soc/amd/mendocino/acpi/pci0.asl +++ b/src/soc/amd/mendocino/acpi/pci0.asl @@ -60,6 +60,8 @@
/* memory space for PCI BARs below 4GB */ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* MMCONF */ + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) })
Method(_CRS, 0) { diff --git a/src/soc/amd/phoenix/acpi/pci0.asl b/src/soc/amd/phoenix/acpi/pci0.asl index 665fe30..f8bc611 100644 --- a/src/soc/amd/phoenix/acpi/pci0.asl +++ b/src/soc/amd/phoenix/acpi/pci0.asl @@ -60,6 +60,8 @@
/* memory space for PCI BARs below 4GB */ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* MMCONF */ + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) })
Method(_CRS, 0) { diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index df21e9d..ad032d6 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -64,6 +64,8 @@
/* memory space for PCI BARs below 4GB */ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* PCIe MMCONF */ + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) }) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) { diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 6a7ed2e..b222f9a 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -90,7 +90,9 @@ Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
/* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* MMCONF */ + Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH) }) /* End Name(_SB.PCI0.CRES) */
Method(_CRS, 0) {