Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10625
-gerrit
commit 6fa57dd8ff73352c2d0afa59792c83814724bc14 Author: Yakir Yang ykk@rock-chips.com Date: Wed Apr 29 10:08:12 2015 -0500
rockchip/rk3288: add support for hdmi display
this is an brief hdmi driver which config with simple display parameter, const encoder input & output color format and 8bit color depth, and only 48KHz audio support.
what's more to prevent TV have not show an right things before coreboot switch to kernel space, we have to add an terrible 2s delay to driver (2s come from test many times), cause we have to wait TV to respond (we got no flag to check whether it is ready).
BUG=chrome-os-partner:40337 TEST=Booted Veyron Jerry and display normal BRANCH=None
Change-Id: Icd33467e95de6219e1b614616f0112afc52097b6 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: 7e5b699aff75a579116aae63d858c834b2f648e8 Original-Change-Id: Iedc87c011c5b62ce5f16a296dd9c3e0c2eaba59b Original-Signed-off-by: Yakir Yang ykk@rock-chips.com Original-Reviewed-on: https://chromium-review.googlesource.com/272565 Original-Reviewed-by: Daniel Kurtz djkurtz@chromium.org Original-Commit-Queue: Lin Huang hl@rock-chips.com Original-Tested-by: Lin Huang hl@rock-chips.com --- src/soc/rockchip/rk3288/Makefile.inc | 1 + src/soc/rockchip/rk3288/chip.h | 1 + src/soc/rockchip/rk3288/clock.c | 11 + src/soc/rockchip/rk3288/display.c | 58 +- src/soc/rockchip/rk3288/hdmi.c | 830 ++++++++++++++++++++++++++++ src/soc/rockchip/rk3288/include/soc/clock.h | 1 + src/soc/rockchip/rk3288/include/soc/hdmi.h | 455 +++++++++++++++ src/soc/rockchip/rk3288/include/soc/vop.h | 7 +- src/soc/rockchip/rk3288/vop.c | 25 +- 9 files changed, 1371 insertions(+), 18 deletions(-)
diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 0b970fd..0ec127b 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -69,6 +69,7 @@ ramstage-y += rk808.c ramstage-y += pwm.c ramstage-y += vop.c ramstage-y += edp.c +ramstage-y += hdmi.c ramstage-y += display.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c
diff --git a/src/soc/rockchip/rk3288/chip.h b/src/soc/rockchip/rk3288/chip.h index 5684520..3a6b14d 100644 --- a/src/soc/rockchip/rk3288/chip.h +++ b/src/soc/rockchip/rk3288/chip.h @@ -29,6 +29,7 @@ struct soc_rockchip_rk3288_config { u32 bl_power_on_udelay; u32 bl_pwm_to_enable_udelay; u32 framebuffer_bits_per_pixel; + u32 vop_mode; };
#endif /* __SOC_ROCKCHIP_RK3288_CHIP_H__ */ diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index a2e8d88..b823e01 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -571,6 +571,17 @@ void rkclk_configure_edp(void) write32(&cru_ptr->cru_softrst_con[6], RK_CLRBITS(1 << 15)); }
+void rkclk_configure_hdmi(void) +{ + /* enable pclk hdmi ctrl */ + write32(&cru_ptr->cru_clkgate_con[16], RK_CLRBITS(1 << 9)); + + /* software reset hdmi */ + write32(&cru_ptr->cru_softrst_con[7], RK_SETBITS(1 << 9)); + udelay(1); + write32(&cru_ptr->cru_softrst_con[7], RK_CLRBITS(1 << 9)); +} + void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) { u32 div; diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 2974d4e..192580b 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -31,6 +31,7 @@ #include <soc/clock.h> #include <soc/display.h> #include <soc/edp.h> +#include <soc/hdmi.h> #include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> @@ -51,15 +52,27 @@ void rk_display_init(device_t dev, u32 lcdbase, dcache_clean_invalidate_by_mva((void *)lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
- rkclk_configure_edp(); + switch (conf->vop_mode) { + case HDMI_MODE: + rkclk_configure_hdmi(); + rkclk_configure_vop_aclk(conf->vop_id, 384 * MHz); + rk_hdmi_init(conf->vop_id); + if (rk_hdmi_get_edid(&edid)) { + printk(BIOS_WARNING, "can not get edid\n"); + return; + } + break;
- rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); - - rk_edp_init(conf->vop_id); - - if (rk_edp_get_edid(&edid)) { - printk(BIOS_WARNING, "can not get edid\n"); - return; + case EDP_MODE: + default: + rkclk_configure_edp(); + rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); + rk_edp_init(conf->vop_id); + if (rk_edp_get_edid(&edid)) { + printk(BIOS_WARNING, "can not get edid\n"); + return; + } + break; }
if (rkclk_configure_vop_dclk(conf->vop_id, edid.pixel_clock * KHz)) { @@ -71,15 +84,34 @@ void rk_display_init(device_t dev, u32 lcdbase, edid.bytes_per_line = edid.ha * conf->framebuffer_bits_per_pixel / 8; edid.x_resolution = edid.ha; edid.y_resolution = edid.va; - rkvop_mode_set(conf->vop_id, &edid); + rkvop_mode_set(conf->vop_id, &edid, conf->vop_mode);
rkvop_enable(conf->vop_id, lcdbase, &edid);
- if (rk_edp_enable()) { - printk(BIOS_WARNING, "edp enable err\n"); - return; + switch (conf->vop_mode) { + case HDMI_MODE: + if (rk_hdmi_enable(&edid)) { + printk(BIOS_WARNING, "hdmi enable err\n"); + return; + } + + /* + * HACK: if we do remove this delay, HDMI TV may not show + * anythings. So we make an delay here, ensure TV have + * enough time to respond. + */ + mdelay(2000); + break; + + case EDP_MODE: + default: + if (rk_edp_enable()) { + printk(BIOS_WARNING, "edp enable err\n"); + return; + } + mainboard_power_on_backlight(); + break; }
set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); - mainboard_power_on_backlight(); } diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c new file mode 100644 index 0000000..ac58fbf --- /dev/null +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -0,0 +1,830 @@ +/* + * Copyright (C) Rockchip, Inc. + * Copyright (C) Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Designware High-Definition Multimedia Interface (HDMI) driveG + */ + +#include <arch/io.h> +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <edid.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <soc/addressmap.h> +#include <soc/hdmi.h> +#include <soc/grf.h> +#include <soc/vop.h> +#include <timer.h> + +#include "chip.h" + +#define AUDIO_SAMPLERATE_DEFAULT (48*KHz) + +#define hdmi_debug(x...) do { if (0) printk(BIOS_DEBUG, x); } while (0) + +struct rk3288_hdmi_regs * const hdmi_regs = (void *)HDMI_TX_BASE; + +struct tmds_n_cts { + u32 tmds; + u32 cts; + u32 n; +}; + +static const struct tmds_n_cts n_cts_table[] = { + { + .tmds = 25175, .n = 6144, .cts = 25175, + }, { + .tmds = 25200, .n = 6144, .cts = 25200, + }, { + .tmds = 27000, .n = 6144, .cts = 27000, + }, { + .tmds = 27027, .n = 6144, .cts = 27027, + }, { + .tmds = 40000, .n = 6144, .cts = 40000, + }, { + .tmds = 54000, .n = 6144, .cts = 54000, + }, { + .tmds = 54054, .n = 6144, .cts = 54054, + }, { + .tmds = 65000, .n = 6144, .cts = 65000, + }, { + .tmds = 74176, .n = 11648, .cts = 140625, + }, { + .tmds = 74250, .n = 6144, .cts = 74250, + }, { + .tmds = 83500, .n = 6144, .cts = 83500, + }, { + .tmds = 106500, .n = 6144, .cts = 106500, + }, { + .tmds = 108000, .n = 6144, .cts = 108000, + }, { + .tmds = 148352, .n = 5824, .cts = 140625, + }, { + .tmds = 148500, .n = 6144, .cts = 148500, + }, { + .tmds = 297000, .n = 5120, .cts = 247500, + } +}; + +struct hdmi_mpll_config { + u64 mpixelclock; + /* Mode of Operation and PLL Dividers Control Register */ + u32 cpce; + /* PLL Gmp Control Register */ + u32 gmp; + /* PLL Current COntrol Register */ + u32 curr; +}; + +struct hdmi_phy_config { + u64 mpixelclock; + u32 sym_ctr; /* clock symbol and transmitter control */ + u32 term; /* transmission termination value */ + u32 vlev_ctr; /* voltage level control */ +}; + +static const struct hdmi_phy_config rockchip_phy_config[] = { + { + .mpixelclock = 74250, + .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272, + }, { + .mpixelclock = 148500, + .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d, + }, { + .mpixelclock = 297000, + .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d, + }, { + .mpixelclock = ~0ul, + .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000, + } +}; + +static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { + { + .mpixelclock = 40000, + .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018, + }, { + .mpixelclock = 65000, + .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, + }, { + .mpixelclock = 66000, + .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038, + }, { + .mpixelclock = 83500, + .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, + }, { + .mpixelclock = 146250, + .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038, + }, { + .mpixelclock = 148500, + .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, + }, { + .mpixelclock = ~0ul, + .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, + } +}; + +static const u32 csc_coeff_default[3][4] = { + { 0x2000, 0x0000, 0x0000, 0x0000 }, + { 0x0000, 0x2000, 0x0000, 0x0000 }, + { 0x0000, 0x0000, 0x2000, 0x0000 } +}; + +static void hdmi_set_clock_regenerator(u32 n, u32 cts) +{ + u8 cts3; + u8 n3; + + /* first set ncts_atomic_write (if present) */ + n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE; + write32(&hdmi_regs->aud_n3, n3); + + /* set cts_manual (if present) */ + cts3 = HDMI_AUD_CTS3_CTS_MANUAL; + + cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET; + cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK; + + /* write cts values; cts3 must be written first */ + write32(&hdmi_regs->aud_cts3, cts3); + write32(&hdmi_regs->aud_cts2, (cts >> 8) & 0xff); + write32(&hdmi_regs->aud_cts1, cts & 0xff); + + /* write n values; n1 must be written last */ + n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK; + write32(&hdmi_regs->aud_n3, n3); + write32(&hdmi_regs->aud_n2, (n >> 8) & 0xff); + write32(&hdmi_regs->aud_n1, n & 0xff); + + write32(&hdmi_regs->aud_inputclkfs, HDMI_AUD_INPUTCLKFS_128); +} + +static int hdmi_lookup_n_cts(u32 pixel_clk) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(n_cts_table); i++) + if (pixel_clk <= n_cts_table[i].tmds) + break; + + if (i >= ARRAY_SIZE(n_cts_table)) + return -1; + + return i; +} + +static void hdmi_audio_set_samplerate(u32 pixel_clk) +{ + u32 clk_n, clk_cts; + int index; + + index = hdmi_lookup_n_cts(pixel_clk); + if (index == -1) { + hdmi_debug("audio not supported for pixel clk %d\n", pixel_clk); + return; + } + + clk_n = n_cts_table[index].n; + clk_cts = n_cts_table[index].cts; + hdmi_set_clock_regenerator(clk_n, clk_cts); +} + +/* + * this submodule is responsible for the video data synchronization. + * for example, for rgb 4:4:4 input, the data map is defined as + * pin{47~40} <==> r[7:0] + * pin{31~24} <==> g[7:0] + * pin{15~8} <==> b[7:0] + */ +static void hdmi_video_sample(void) +{ + u32 color_format = 0x01; + u8 val; + + val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | + ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & + HDMI_TX_INVID0_VIDEO_MAPPING_MASK); + + write32(&hdmi_regs->tx_invid0, val); + + /* enable tx stuffing: when de is inactive, fix the output data to 0 */ + val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; + write32(&hdmi_regs->tx_instuffing, val); + write32(&hdmi_regs->tx_gydata0, 0x0); + write32(&hdmi_regs->tx_gydata1, 0x0); + write32(&hdmi_regs->tx_rcrdata0, 0x0); + write32(&hdmi_regs->tx_rcrdata1, 0x0); + write32(&hdmi_regs->tx_bcbdata0, 0x0); + write32(&hdmi_regs->tx_bcbdata1, 0x0); +} + +static void hdmi_update_csc_coeffs(void) +{ + u32 i, j; + u32 csc_scale = 1; + + /* the csc registers are sequential, alternating msb then lsb */ + for (i = 0; i < ARRAY_SIZE(csc_coeff_default); i++) { + for (j = 0; j < ARRAY_SIZE(csc_coeff_default[0]); j++) { + u32 coeff = csc_coeff_default[i][j]; + write32(&hdmi_regs->csc_coef[i][j].msb, coeff >> 8); + write32(&hdmi_regs->csc_coef[i][j].lsb, coeff && 0xff); + } + } + + clrsetbits_le32(&hdmi_regs->csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, + csc_scale); +} + +static void hdmi_video_csc(void) +{ + u32 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; + u32 interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; + + /* configure the csc registers */ + write32(&hdmi_regs->csc_cfg, interpolation); + clrsetbits_le32(&hdmi_regs->csc_scale, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, color_depth); + + hdmi_update_csc_coeffs(); +} + +static void hdmi_video_packetize(void) +{ + u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; + u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT; + u32 color_depth = 0; + u8 val, vp_conf; + + /* set the packetizer registers */ + val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & + HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | + ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); + write32(&hdmi_regs->vp_pr_cd, val); + + clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); + + /* data from pixel repeater block */ + vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; + + clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_PR_EN_MASK | + HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); + + clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, + 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); + + write32(&hdmi_regs->vp_remap, remap_size); + + vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | + HDMI_VP_CONF_PP_EN_DISABLE | + HDMI_VP_CONF_YCC422_EN_DISABLE; + + clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | + HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, + vp_conf); + + clrsetbits_le32(&hdmi_regs->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | + HDMI_VP_STUFF_YCC422_STUFFING_MASK, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); + + clrsetbits_le32(&hdmi_regs->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, + output_select); +} + +static inline void hdmi_phy_test_clear(u8 bit) +{ + clrsetbits_le32(&hdmi_regs->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, + bit << HDMI_PHY_TST0_TSTCLR_OFFSET); +} + +static int hdmi_phy_wait_i2c_done(u32 msec) +{ + struct stopwatch phyi2c_done; + u32 val; + + stopwatch_init_msecs_expire(&phyi2c_done, msec); + do { + val = read32(&hdmi_regs->ih_i2cmphy_stat0); + if (val & 0x3) { + write32(&hdmi_regs->ih_i2cmphy_stat0, val); + return 0; + } + + udelay(100); + } while (!stopwatch_expired(&phyi2c_done)); + + return 1; +} + +static void hdmi_phy_i2c_write(u16 data, u8 addr) +{ + write32(&hdmi_regs->ih_i2cmphy_stat0, 0xff); + write32(&hdmi_regs->phy_i2cm_address_addr, addr); + write32(&hdmi_regs->phy_i2cm_datao_1_addr, (u8)(data >> 8)); + write32(&hdmi_regs->phy_i2cm_datao_0_addr, (u8)(data >> 0)); + write32(&hdmi_regs->phy_i2cm_operation_addr, + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE); + + hdmi_phy_wait_i2c_done(1000); +} + +static void hdmi_phy_enable_power(u8 enable) +{ + clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, + enable << HDMI_PHY_CONF0_PDZ_OFFSET); +} + +static void hdmi_phy_enable_tmds(u8 enable) +{ + clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, + enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); +} + +static void hdmi_phy_enable_spare(u8 enable) +{ + clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, + enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); +} + +static void hdmi_phy_gen2_pddq(u8 enable) +{ + clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, + enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); +} + +static void hdmi_phy_gen2_txpwron(u8 enable) +{ + clrsetbits_le32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, + enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); +} + +static void hdmi_phy_sel_data_en_pol(u8 enable) +{ + clrsetbits_le32(&hdmi_regs->phy_conf0, + HDMI_PHY_CONF0_SELDATAENPOL_MASK, + enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); +} + +static void hdmi_phy_sel_interface_control(u8 enable) +{ + clrsetbits_le32(&hdmi_regs->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, + enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); +} + +static int hdmi_phy_configure(u32 mpixelclock) +{ + struct stopwatch pll_ready; + u8 i, val; + + write32(&hdmi_regs->mc_flowctrl, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS); + + /* gen2 tx power off */ + hdmi_phy_gen2_txpwron(0); + + /* gen2 pddq */ + hdmi_phy_gen2_pddq(1); + + /* phy reset */ + write32(&hdmi_regs->mc_phyrstz, HDMI_MC_PHYRSTZ_DEASSERT); + write32(&hdmi_regs->mc_phyrstz, HDMI_MC_PHYRSTZ_ASSERT); + write32(&hdmi_regs->mc_heacphy_rst, HDMI_MC_HEACPHY_RST_ASSERT); + + hdmi_phy_test_clear(1); + write32(&hdmi_regs->phy_i2cm_slave_addr, + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); + hdmi_phy_test_clear(0); + + /* pll/mpll cfg - always match on final entry */ + for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++) + if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock) + break; + + hdmi_phy_i2c_write(rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG); + hdmi_phy_i2c_write(rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL); + hdmi_phy_i2c_write(rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL); + + hdmi_phy_i2c_write(0x0000, PHY_PLLPHBYCTRL); + hdmi_phy_i2c_write(0x0006, PHY_PLLCLKBISTPHASE); + + for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++) + if (mpixelclock <= rockchip_phy_config[i].mpixelclock) + break; + + /* + * resistance term 133ohm cfg + * preemp cgf 0.00 + * tx/ck lvl 10 + */ + hdmi_phy_i2c_write(rockchip_phy_config[i].term, PHY_TXTERM); + hdmi_phy_i2c_write(rockchip_phy_config[i].sym_ctr, PHY_CKSYMTXCTRL); + hdmi_phy_i2c_write(rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL); + + /* remove clk term */ + hdmi_phy_i2c_write(0x8000, PHY_CKCALCTRL); + + hdmi_phy_enable_power(1); + + /* toggle tmds enable */ + hdmi_phy_enable_tmds(0); + hdmi_phy_enable_tmds(1); + + /* gen2 tx power on */ + hdmi_phy_gen2_txpwron(1); + hdmi_phy_gen2_pddq(0); + + hdmi_phy_enable_spare(1); + + /* wait for phy pll lock */ + stopwatch_init_msecs_expire(&pll_ready, 5); + do { + val = read32(&hdmi_regs->phy_stat0); + if (!(val & HDMI_PHY_TX_PHY_LOCK)) + return 0; + + udelay(100); + } while (!stopwatch_expired(&pll_ready)); + + return -1; +} + +static int hdmi_phy_init(u32 mpixelclock) +{ + int i, ret; + + /* hdmi phy spec says to do the phy initialization sequence twice */ + for (i = 0; i < 2; i++) { + hdmi_phy_sel_data_en_pol(1); + hdmi_phy_sel_interface_control(0); + hdmi_phy_enable_tmds(0); + hdmi_phy_enable_power(0); + + /* enable csc */ + ret = hdmi_phy_configure(mpixelclock); + if (ret) { + hdmi_debug("hdmi phy config failure %d\n", ret); + return ret; + } + } + + return 0; +} + +static void hdmi_av_composer(const struct edid *edid) +{ + u8 mdataenablepolarity = 1; + u8 mdvi = 0; + u8 inv_val; + + /* set up hdmi_fc_invidconf */ + inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE; + + inv_val |= (edid->pvsync ? + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); + + inv_val |= (edid->phsync ? + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); + + inv_val |= (mdataenablepolarity ? + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); + + inv_val |= (mdvi ? + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE : + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE); + + inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; + + inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; + + write32(&hdmi_regs->fc_invidconf, inv_val); + + /* set up horizontal active pixel width */ + write32(&hdmi_regs->fc_inhactv1, edid->ha >> 8); + write32(&hdmi_regs->fc_inhactv0, edid->ha); + + /* set up vertical active lines */ + write32(&hdmi_regs->fc_invactv1, edid->va >> 8); + write32(&hdmi_regs->fc_invactv0, edid->va); + + /* set up horizontal blanking pixel region width */ + write32(&hdmi_regs->fc_inhblank1, edid->hbl >> 8); + write32(&hdmi_regs->fc_inhblank0, edid->hbl); + + /* set up vertical blanking pixel region width */ + write32(&hdmi_regs->fc_invblank, edid->vbl); + + /* set up hsync active edge delay width (in pixel clks) */ + write32(&hdmi_regs->fc_hsyncindelay1, edid->hso >> 8); + write32(&hdmi_regs->fc_hsyncindelay0, edid->hso); + + /* set up vsync active edge delay (in lines) */ + write32(&hdmi_regs->fc_vsyncindelay, edid->vso); + + /* set up hsync active pulse width (in pixel clks) */ + write32(&hdmi_regs->fc_hsyncinwidth1, edid->hspw >> 8); + write32(&hdmi_regs->fc_hsyncinwidth0, edid->hspw); + + /* set up vsync active edge delay (in lines) */ + write32(&hdmi_regs->fc_vsyncinwidth, edid->vspw); +} + +/* hdmi initialization step b.4 */ +static void hdmi_enable_video_path(void) +{ + u8 clkdis; + + /* control period minimum duration */ + write32(&hdmi_regs->fc_ctrldur, 12); + write32(&hdmi_regs->fc_exctrldur, 32); + write32(&hdmi_regs->fc_exctrlspac, 1); + + /* set to fill tmds data channels */ + write32(&hdmi_regs->fc_ch0pream, 0x0b); + write32(&hdmi_regs->fc_ch1pream, 0x16); + write32(&hdmi_regs->fc_ch2pream, 0x21); + + /* enable pixel clock and tmds data path */ + clkdis = 0x7f; + clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; + write32(&hdmi_regs->mc_clkdis, clkdis); + + clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; + write32(&hdmi_regs->mc_clkdis, clkdis); + + clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; + write32(&hdmi_regs->mc_clkdis, clkdis); +} + +/* workaround to clear the overflow condition */ +static void hdmi_clear_overflow(void) +{ + u8 val, count; + + /* tmds software reset */ + write32(&hdmi_regs->mc_swrstz, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ); + + val = read32(&hdmi_regs->fc_invidconf); + + for (count = 0; count < 4; count++) + write32(&hdmi_regs->fc_invidconf, val); +} + +static void hdmi_audio_set_format(void) +{ + write32(&hdmi_regs->aud_conf0, + HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0); + + write32(&hdmi_regs->aud_conf1, + HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE | + HDMI_AUD_CONF1_I2S_WIDTH_16BIT); + + write32(&hdmi_regs->aud_conf2, 0x00); +} + +static void hdmi_audio_fifo_reset(void) +{ + write32(&hdmi_regs->mc_swrstz, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ); + write32(&hdmi_regs->aud_conf0, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST); + + write32(&hdmi_regs->aud_int, 0x00); + write32(&hdmi_regs->aud_int1, 0x00); +} + +static int hdmi_setup(const struct edid *edid) +{ + int ret; + + hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n", + edid->pixel_clock, edid->ha, edid->va); + + hdmi_av_composer(edid); + + ret = hdmi_phy_init(edid->pixel_clock); + if (ret) + return ret; + + hdmi_enable_video_path(); + + hdmi_audio_fifo_reset(); + hdmi_audio_set_format(); + hdmi_audio_set_samplerate(edid->pixel_clock); + + hdmi_video_packetize(); + hdmi_video_csc(); + hdmi_video_sample(); + + hdmi_clear_overflow(); + + return 0; +} + +static void hdmi_init_interrupt(void) +{ + u8 ih_mute; + + /* + * boot up defaults are: + * hdmi_ih_mute = 0x03 (disabled) + * hdmi_ih_mute_* = 0x00 (enabled) + * + * disable top level interrupt bits in hdmi block + */ + ih_mute = read32(&hdmi_regs->ih_mute) | + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; + + write32(&hdmi_regs->ih_mute, ih_mute); + + /* enable i2c master done irq */ + write32(&hdmi_regs->i2cm_int, ~0x04); + + /* enable i2c client nack % arbitration error irq */ + write32(&hdmi_regs->i2cm_ctlint, ~0x44); + + /* enable phy i2cm done irq */ + write32(&hdmi_regs->phy_i2cm_int_addr, HDMI_PHY_I2CM_INT_ADDR_DONE_POL); + + /* enable phy i2cm nack & arbitration error irq */ + write32(&hdmi_regs->phy_i2cm_ctlint_addr, + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL); + + /* enable cable hot plug irq */ + write32(&hdmi_regs->phy_mask0, (u8)~HDMI_PHY_HPD); + + /* clear hotplug interrupts */ + write32(&hdmi_regs->ih_phy_stat0, HDMI_IH_PHY_STAT0_HPD); +} + +static u8 hdmi_get_plug_in_status(void) +{ + u8 val = read32(&hdmi_regs->phy_stat0) & HDMI_PHY_HPD; + + return !!(val); +} + +static int hdmi_wait_for_hpd(void) +{ + struct stopwatch hpd; + + stopwatch_init_msecs_expire(&hpd, 30000); + do { + if (hdmi_get_plug_in_status()) + return 0; + udelay(100); + } while (!stopwatch_expired(&hpd)); + + return -1; +} + +static int hdmi_ddc_wait_i2c_done(int msec) +{ + struct stopwatch ddci2c_done; + u32 val; + + stopwatch_init_msecs_expire(&ddci2c_done, msec); + do { + val = read32(&hdmi_regs->ih_i2cm_stat0); + if (val & 0x2) { + write32(&hdmi_regs->ih_i2cm_stat0, val); + return 0; + } + + udelay(100); + } while (!stopwatch_expired(&ddci2c_done)); + + return 1; +} + +static void hdmi_ddc_reset(void) +{ + clrsetbits_le32(&hdmi_regs->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ, + HDMI_I2CM_SOFTRSTZ); +} + +static int hdmi_read_edid(int block, u8 *buff) +{ + int shift = (block % 2) * 0x80; + int edid_read_err = 0; + u32 trytime = 5; + u32 n, j, val; + + /* set ddc i2c clk which devided from ddc_clk to 100khz */ + write32(&hdmi_regs->i2cm_ss_scl_hcnt_0_addr, 0x7a); + write32(&hdmi_regs->i2cm_ss_scl_lcnt_0_addr, 0x8d); + clrsetbits_le32(&hdmi_regs->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, + HDMI_I2CM_DIV_STD_MODE); + + write32(&hdmi_regs->i2cm_slave, HDMI_I2CM_SLAVE_DDC_ADDR); + write32(&hdmi_regs->i2cm_segaddr, HDMI_I2CM_SEGADDR_DDC); + write32(&hdmi_regs->i2cm_segptr, block >> 1); + + while (trytime--) { + for (n = 0; n < HDMI_EDID_BLOCK_SIZE/8; n++) { + write32(&hdmi_regs->i2cmess, shift + 8 * n); + + if (block == 0) + clrsetbits_le32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8, + HDMI_I2CM_OPT_RD8); + else + clrsetbits_le32(&hdmi_regs->i2cm_operation, + HDMI_I2CM_OPT_RD8_EXT, + HDMI_I2CM_OPT_RD8_EXT); + + if (hdmi_ddc_wait_i2c_done(10)) { + hdmi_ddc_reset(); + edid_read_err = 1; + break; + } + + for (j = 0; j < 8; j++) { + val = read32(&hdmi_regs->i2cm_buf0 + j); + buff[8 * n + j] = val; + } + } + + if (!edid_read_err) + break; + + edid_read_err = 0; + } + + return edid_read_err; +} + +int rk_hdmi_get_edid(struct edid *edid) +{ + u8 edid_buf[HDMI_EDID_BLOCK_SIZE * 2]; + u32 edid_size = HDMI_EDID_BLOCK_SIZE; + int ret; + + ret = hdmi_read_edid(0, edid_buf); + if (ret) { + hdmi_debug("failed to read edid.\n"); + return -1; + } + + if (edid_buf[0x7e] != 0) { + hdmi_read_edid(1, edid_buf + HDMI_EDID_BLOCK_SIZE); + edid_size += HDMI_EDID_BLOCK_SIZE; + } + + ret = decode_edid(edid_buf, edid_size, edid); + if (ret) { + hdmi_debug("failed to decode edid.\n"); + return -1; + } + + return 0; +} + +int rk_hdmi_enable(const struct edid *edid) +{ + hdmi_setup(edid); + + return 0; +} + +int rk_hdmi_init(u32 vop_id) +{ + int ret; + u32 val; + + /* hdmi source select hdmi controller */ + write32(&rk3288_grf->soc_con6, RK_SETBITS(1 << 15)); + + /* hdmi data from vop id */ + val = (vop_id == 1) ? RK_SETBITS(1 << 4) : RK_CLRBITS(1 << 4); + write32(&rk3288_grf->soc_con6, val); + + ret = hdmi_wait_for_hpd(); + if (ret < 0) { + hdmi_debug("hdmi can not get hpd signal\n"); + return -1; + } + + hdmi_init_interrupt(); + + hdmi_debug("hdmi init success\n"); + + return 0; +} diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h index 51735cc..08d9d45 100644 --- a/src/soc/rockchip/rk3288/include/soc/clock.h +++ b/src/soc/rockchip/rk3288/include/soc/clock.h @@ -50,5 +50,6 @@ void rkclk_configure_tsadc(unsigned int hz); void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); void rkclk_configure_edp(void); +void rkclk_configure_hdmi(void); int rkclk_was_watchdog_reset(void); #endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h new file mode 100644 index 0000000..70856e0 --- /dev/null +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -0,0 +1,455 @@ +/* + * Copyright (C) 2015 Rockchip, Inc. + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __SOC_HDMI_H__ +#define __SOC_HDMI_H__ + +#include <types.h> +#include <stdlib.h> + +#define HDMI_EDID_BLOCK_SIZE 128 + +struct rk3288_hdmi_regs { + u32 reserved0[0x100]; + u32 ih_fc_stat0; + u32 ih_fc_stat1; + u32 ih_fc_stat2; + u32 ih_as_stat0; + u32 ih_phy_stat0; + u32 ih_i2cm_stat0; + u32 ih_cec_stat0; + u32 ih_vp_stat0; + u32 ih_i2cmphy_stat0; + u32 ih_ahbdmaaud_stat0; + u32 reserved1[0x17f-0x109]; + u32 ih_mute_fc_stat0; + u32 ih_mute_fc_stat1; + u32 ih_mute_fc_stat2; + u32 ih_mute_as_stat0; + u32 ih_mute_phy_stat0; + u32 ih_mute_i2cm_stat0; + u32 ih_mute_cec_stat0; + u32 ih_mute_vp_stat0; + u32 ih_mute_i2cmphy_stat0; + u32 ih_mute_ahbdmaaud_stat0; + u32 reserved2[0x1fe - 0x189]; + u32 ih_mute; + u32 tx_invid0; + u32 tx_instuffing; + u32 tx_gydata0; + u32 tx_gydata1; + u32 tx_rcrdata0; + u32 tx_rcrdata1; + u32 tx_bcbdata0; + u32 tx_bcbdata1; + u32 reserved3[0x7ff-0x207]; + u32 vp_status; + u32 vp_pr_cd; + u32 vp_stuff; + u32 vp_remap; + u32 vp_conf; + u32 vp_stat; + u32 vp_int; + u32 vp_mask; + u32 vp_pol; + u32 reserved4[0xfff-0x808]; + u32 fc_invidconf; + u32 fc_inhactv0; + u32 fc_inhactv1; + u32 fc_inhblank0; + u32 fc_inhblank1; + u32 fc_invactv0; + u32 fc_invactv1; + u32 fc_invblank; + u32 fc_hsyncindelay0; + u32 fc_hsyncindelay1; + u32 fc_hsyncinwidth0; + u32 fc_hsyncinwidth1; + u32 fc_vsyncindelay; + u32 fc_vsyncinwidth; + u32 fc_infreq0; + u32 fc_infreq1; + u32 fc_infreq2; + u32 fc_ctrldur; + u32 fc_exctrldur; + u32 fc_exctrlspac; + u32 fc_ch0pream; + u32 fc_ch1pream; + u32 fc_ch2pream; + u32 fc_aviconf3; + u32 fc_gcp; + u32 fc_aviconf0; + u32 fc_aviconf1; + u32 fc_aviconf2; + u32 fc_avivid; + u32 fc_avietb0; + u32 fc_avietb1; + u32 fc_avisbb0; + u32 fc_avisbb1; + u32 fc_avielb0; + u32 fc_avielb1; + u32 fc_avisrb0; + u32 fc_avisrb1; + u32 fc_audiconf0; + u32 fc_audiconf1; + u32 fc_audiconf2; + u32 fc_audiconf3; + u32 fc_vsdieeeid0; + u32 fc_vsdsize; + u32 reserved7[0x2fff-0x102a]; + u32 phy_conf0; + u32 phy_tst0; + u32 phy_tst1; + u32 phy_tst2; + u32 phy_stat0; + u32 phy_int0; + u32 phy_mask0; + u32 phy_pol0; + u32 reserved8[0x301f-0x3007]; + u32 phy_i2cm_slave_addr; + u32 phy_i2cm_address_addr; + u32 phy_i2cm_datao_1_addr; + u32 phy_i2cm_datao_0_addr; + u32 phy_i2cm_datai_1_addr; + u32 phy_i2cm_datai_0_addr; + u32 phy_i2cm_operation_addr; + u32 phy_i2cm_int_addr; + u32 phy_i2cm_ctlint_addr; + u32 phy_i2cm_div_addr; + u32 phy_i2cm_softrstz_addr; + u32 phy_i2cm_ss_scl_hcnt_1_addr; + u32 phy_i2cm_ss_scl_hcnt_0_addr; + u32 phy_i2cm_ss_scl_lcnt_1_addr; + u32 phy_i2cm_ss_scl_lcnt_0_addr; + u32 phy_i2cm_fs_scl_hcnt_1_addr; + u32 phy_i2cm_fs_scl_hcnt_0_addr; + u32 phy_i2cm_fs_scl_lcnt_1_addr; + u32 phy_i2cm_fs_scl_lcnt_0_addr; + u32 reserved9[0x30ff-0x3032]; + u32 aud_conf0; + u32 aud_conf1; + u32 aud_int; + u32 aud_conf2; + u32 aud_int1; + u32 reserved32[0x31ff-0x3104]; + u32 aud_n1; + u32 aud_n2; + u32 aud_n3; + u32 aud_cts1; + u32 aud_cts2; + u32 aud_cts3; + u32 aud_inputclkfs; + u32 reserved12[0x3fff-0x3206]; + u32 mc_sfrdiv; + u32 mc_clkdis; + u32 mc_swrstz; + u32 mc_opctrl; + u32 mc_flowctrl; + u32 mc_phyrstz; + u32 mc_lockonclock; + u32 mc_heacphy_rst; + u32 reserved13[0x40ff-0x4007]; + u32 csc_cfg; + u32 csc_scale; + struct { + u32 msb; + u32 lsb; + } csc_coef[3][4]; + u32 reserved17[0x7dff-0x4119]; + u32 i2cm_slave; + u32 i2cmess; + u32 i2cm_datao; + u32 i2cm_datai; + u32 i2cm_operation; + u32 i2cm_int; + u32 i2cm_ctlint; + u32 i2cm_div; + u32 i2cm_segaddr; + u32 i2cm_softrstz; + u32 i2cm_segptr; + u32 i2cm_ss_scl_hcnt_1_addr; + u32 i2cm_ss_scl_hcnt_0_addr; + u32 i2cm_ss_scl_lcnt_1_addr; + u32 i2cm_ss_scl_lcnt_0_addr; + u32 i2cm_fs_scl_hcnt_1_addr; + u32 i2cm_fs_scl_hcnt_0_addr; + u32 i2cm_fs_scl_lcnt_1_addr; + u32 i2cm_fs_scl_lcnt_0_addr; + u32 reserved18[0x7e1f-0x7e12]; + u32 i2cm_buf0; +}; +check_member(rk3288_hdmi_regs, i2cm_buf0, 0x1f880); + +enum { + /* HDMI PHY registers define */ + PHY_OPMODE_PLLCFG = 0x06, + PHY_CKCALCTRL = 0x05, + PHY_CKSYMTXCTRL = 0x09, + PHY_VLEVCTRL = 0x0e, + PHY_PLLCURRCTRL = 0x10, + PHY_PLLPHBYCTRL = 0x13, + PHY_PLLGMPCTRL = 0x15, + PHY_PLLCLKBISTPHASE = 0x17, + PHY_TXTERM = 0x19, + + /* ih_phy_stat0 field values */ + HDMI_IH_PHY_STAT0_HPD = 0x1, + + /* ih_mute field values */ + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, + + /* tx_invid0 field values */ + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, + HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, + HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, + + /* tx_instuffing field values */ + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, + + /* vp_pr_cd field values */ + HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, + HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, + + /* vp_stuff field values */ + HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, + HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, + HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, + HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, + HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, + + /* vp_conf field values */ + HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, + HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, + HDMI_VP_CONF_PP_EN_ENMASK = 0x20, + HDMI_VP_CONF_PP_EN_DISABLE = 0x00, + HDMI_VP_CONF_PR_EN_MASK = 0x10, + HDMI_VP_CONF_PR_EN_DISABLE = 0x00, + HDMI_VP_CONF_YCC422_EN_MASK = 0x8, + HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, + HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, + HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, + + /* vp_remap field values */ + HDMI_VP_REMAP_YCC422_16BIT = 0x0, + + /* fc_invidconf field values */ + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, + HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, + + + /* fc_aviconf0-fc_aviconf3 field values */ + HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, + HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, + HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, + HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, + HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, + HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, + HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, + HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, + HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, + HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, + + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, + HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, + HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, + HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, + HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, + HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, + + HDMI_FC_AVICONF2_SCALING_MASK = 0x03, + HDMI_FC_AVICONF2_SCALING_NONE = 0x00, + HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, + HDMI_FC_AVICONF2_SCALING_VERT = 0x02, + HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, + HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, + HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, + HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, + HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, + HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, + HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, + HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, + + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, + HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, + + /* fc_gcp field values*/ + HDMI_FC_GCP_SET_AVMUTE = 0x02, + HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, + + /* phy_conf0 field values */ + HDMI_PHY_CONF0_PDZ_MASK = 0x80, + HDMI_PHY_CONF0_PDZ_OFFSET = 7, + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, + HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, + HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, + HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, + HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, + HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, + HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, + + /* phy_tst0 field values */ + HDMI_PHY_TST0_TSTCLR_MASK = 0x20, + HDMI_PHY_TST0_TSTCLR_OFFSET = 5, + + /* phy_stat0 field values */ + HDMI_PHY_HPD = 0x02, + HDMI_PHY_TX_PHY_LOCK = 0x01, + + /* phy_i2cm_slave_addr field values */ + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, + + /* phy_i2cm_operation_addr field values */ + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, + + /* hdmi_phy_i2cm_int_addr */ + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, + + /* hdmi_phy_i2cm_ctlint_addr */ + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, + + /* aud_conf0 field values */ + HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, + HDMI_AUD_CONF0_I2S_SELECT = 0x20, + HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, + HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, + HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, + HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, + + /* aud_conf0 field values */ + HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, + HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, + + /* aud_n3 field values */ + HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, + HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, + + /* aud_cts3 field values */ + HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, + HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, + HDMI_AUD_CTS3_N_SHIFT_1 = 0, + HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, + HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, + HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, + HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, + HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, + HDMI_AUD_CTS3_CTS_MANUAL = 0x10, + HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, + + /* aud_inputclkfs filed values */ + HDMI_AUD_INPUTCLKFS_128 = 0x0, + + /* mc_clkdis field values */ + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + + /* mc_swrstz field values */ + HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, + + /* mc_flowctrl field values */ + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, + + /* mc_phyrstz field values */ + HDMI_MC_PHYRSTZ_ASSERT = 0x0, + HDMI_MC_PHYRSTZ_DEASSERT = 0x1, + + /* mc_heacphy_rst field values */ + HDMI_MC_HEACPHY_RST_ASSERT = 0x1, + + /* csc_cfg field values */ + HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, + + /* csc_scale field values */ + HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, + HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, + HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, + + /* i2cm filed values */ + HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, + HDMI_I2CM_SEGADDR_DDC = 0x30, + HDMI_I2CM_OPT_RD8_EXT = 0x8, + HDMI_I2CM_OPT_RD8 = 0x4, + HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, + HDMI_I2CM_DIV_FAST_MODE = 0x8, + HDMI_I2CM_DIV_STD_MODE = 0x0, + HDMI_I2CM_SOFTRSTZ = 0x1, +}; + +int rk_hdmi_init(u32 vop_id); +int rk_hdmi_enable(const struct edid *edid); +int rk_hdmi_get_edid(struct edid *edid); + +#endif /* __SOC_HDMI_H__ */ diff --git a/src/soc/rockchip/rk3288/include/soc/vop.h b/src/soc/rockchip/rk3288/include/soc/vop.h index 89c1dbc..6cb883a 100644 --- a/src/soc/rockchip/rk3288/include/soc/vop.h +++ b/src/soc/rockchip/rk3288/include/soc/vop.h @@ -100,6 +100,11 @@ enum { LB_RGB_1280X8 = 0x5 };
+enum { + EDP_MODE, + HDMI_MODE, +}; + /* VOP_VERSION_INFO */ #define M_FPGA_VERSION (0xffff << 16) #define M_RTL_VERSION (0xffff) @@ -351,6 +356,6 @@ enum { #define V_VAEP(x) (((x)&0x1fff)<<0) #define V_VASP(x) (((x)&0x1fff)<<16)
-void rkvop_mode_set(u32 vop_id, const struct edid *edid); +void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode); void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid); #endif diff --git a/src/soc/rockchip/rk3288/vop.c b/src/soc/rockchip/rk3288/vop.c index 04a7b0f..03338e8 100644 --- a/src/soc/rockchip/rk3288/vop.c +++ b/src/soc/rockchip/rk3288/vop.c @@ -96,7 +96,7 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) write32(&preg->reg_cfg_done, 0x01); /* enable reg config */ }
-void rkvop_mode_set(u32 vop_id, const struct edid *edid) +void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) { u32 hactive = edid->ha; u32 vactive = edid->va; @@ -108,9 +108,26 @@ void rkvop_mode_set(u32 vop_id, const struct edid *edid) u32 vback_porch = edid->vbl - edid->vso - edid->vspw; struct rk3288_vop_regs *preg = vop_regs[vop_id];
- clrsetbits_le32(&preg->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1)); - clrsetbits_le32(&preg->dsp_ctrl0, M_DSP_OUT_MODE, - V_DSP_OUT_MODE(15)); + switch (mode) { + + case HDMI_MODE: + clrsetbits_le32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); + break; + + case EDP_MODE: + default: + clrsetbits_le32(&preg->sys_ctrl, + M_ALL_OUT_EN, V_EDP_OUT_EN(1)); + break; + } + + clrsetbits_le32(&preg->dsp_ctrl0, + M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, + V_DSP_OUT_MODE(15) | + V_DSP_HSYNC_POL(!!edid->phsync) | + V_DSP_VSYNC_POL(!!edid->pvsync)); + write32(&preg->dsp_htotal_hs_end, V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch));