[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add support for LPSS UART in ACPI mode

[Patrick Rudolph (Code Review)]

Hello Philipp Deppenwiese, [e-mail], build bot (Jenkins), Justin van Son, Patrick Georgi, Martin Roth, Paul Menzel, Christian Walter, Angel Pons,  Marcello Sylvester Bauer, Patrick Rudolph, Stef van Os,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40405

to look at the new patch set (#20).

Change subject: soc/intel/common: Add support for LPSS UART in ACPI mode
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soc/intel/common: Add support for LPSS UART in ACPI mode

Emit ACPI code for LPSS UARTs operating in ACPI mode. In this mode the
device vendor ID reads as 0xffff, the PCI devices is still operate.

Add ACPI device IDs for APL, GLK, SPT, SPT_H and CNP_H.

The mainboard's devicetree needs to be adapted to include the chip driver
and the PCI ID when it wouldn't been have hidden.

Example:
 chip soc/intel/common/block/uart
  device pci 19.2 hidden
   register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
  end # UART #2
 end

Tested on Linux 5.6 with Sunrise Point ACPI ID for UART2.
Tested on Windows for all other UARTs.

Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96
Signed-off-by: Patrick Rudolph 
---
A src/soc/intel/common/block/uart/chip.h
M src/soc/intel/common/block/uart/uart.c
2 files changed, 174 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40405/20