Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29678
Change subject: soc/intel/.../Kconfig: Move GPIO debug option into debug menu ......................................................................
soc/intel/.../Kconfig: Move GPIO debug option into debug menu
Rename DEBUG_SOC_COMMON_BLOCK_GPIO to DEBUG_GPIO and move it into the Debugging menu.
Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c Signed-off-by: Nico Huber nico.h@gmx.de --- M src/Kconfig M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/denverton_ns/Kconfig 4 files changed, 11 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/29678/1
diff --git a/src/Kconfig b/src/Kconfig index 0b97125..ce584f5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -693,6 +693,13 @@ help If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
+config HAVE_DEBUG_GPIO + bool + +config DEBUG_GPIO + bool "Output verbose GPIO debug messages" + depends on HAVE_DEBUG_GPIO + config DEBUG_CBFS bool "Output verbose CBFS debug messages" default n diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index 66cc182..bdbc323 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -1,15 +1,9 @@ config SOC_INTEL_COMMON_BLOCK_GPIO bool + select HAVE_DEBUG_GPIO help Intel Processor common GPIO support
-config DEBUG_SOC_COMMON_BLOCK_GPIO - depends on SOC_INTEL_COMMON_BLOCK_GPIO - bool "Output verbose GPIO debug messages" - default n - help - This option enables GPIO debug messages - # Use to program Interrupt Polarity Control (IPCx) register # Each bit represents IRQx Active High Polarity Disable configuration: # when set to 1, the interrupt polarity associated with IRQx is inverted diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index bd12477..9b6ca7e 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -265,7 +265,7 @@ soc_pad_conf &= mask[i]; soc_pad_conf |= pad_conf & ~mask[i];
- if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) + if (IS_ENABLED(CONFIG_DEBUG_GPIO)) printk(BIOS_DEBUG, "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x" " : 0x%08x]\n", @@ -533,7 +533,7 @@ MISCCFG_GPE0_DW1_MASK | MISCCFG_GPE0_DW0_MASK);
- if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) + if (IS_ENABLED(CONFIG_DEBUG_GPIO)) printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n", misccfg_mask, misccfg_value); comm = soc_gpio_get_community(&gpio_communities); diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index d9490cb..5b704b9 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -29,6 +29,7 @@ select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES + select DEBUG_GPIO select POSTCAR_CONSOLE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET @@ -50,7 +51,6 @@ # select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO - select DEBUG_SOC_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER