Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73504 )
Change subject: soc/amd/*/acpi: factor out common generate_cpu_entries implementation ......................................................................
soc/amd/*/acpi: factor out common generate_cpu_entries implementation
With the exception of the generate_cppc_entries call, the implementations of generate_cpu_entries of Picasso, Cezanne, Mendocino, Phoenix and Glinda are identical, so factor it out and move it to the common AMD SoC code. Since all SoCs that support CPPC already select the SOC_AMD_COMMON_BLOCK_ACPI_CPPC Kconfig option, this can be used to only call generate_cppc_entries for platforms where it is available.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I71323d9d071b6f9d82852479b60dc56c24f2b9ec --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/acpi/cpu_power_state.c M src/soc/amd/common/block/include/amdblocks/cpu.h M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c 7 files changed, 85 insertions(+), 283 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/73504/1
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 8845529..51c62cb 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -184,8 +184,8 @@ /* * Populate structure describing enabled p-states and return count of enabled p-states. */ -static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, - struct acpi_xpss_sw_pstate *pstate_xpss_values) +size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, + struct acpi_xpss_sw_pstate *pstate_xpss_values) { msr_t pstate_def; size_t pstate_count, pstate; @@ -246,58 +246,3 @@ *size = ARRAY_SIZE(cstate_cfg_table); return cstate_cfg_table; } - -void generate_cpu_entries(const struct device *device) -{ - int logical_cores; - size_t cstate_count, pstate_count, cpu; - acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} }; - struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; - struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; - uint32_t threads_per_core; - - const acpi_addr_t perf_ctrl = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_CTL_REG, - }; - const acpi_addr_t perf_sts = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_STS_REG, - }; - - threads_per_core = get_threads_per_core(); - cstate_count = get_cstate_info(cstate_values); - pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); - logical_cores = get_cpu_count(); - - for (cpu = 0; cpu < logical_cores; cpu++) { - acpigen_write_processor_device(cpu); - - acpigen_write_pct_package(&perf_ctrl, &perf_sts); - - acpigen_write_pss_object(pstate_values, pstate_count); - - acpigen_write_xpss_object(pstate_xpss_values, pstate_count); - - if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) - acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, - HW_ALL); - else - acpigen_write_PSD_package(0, logical_cores, SW_ALL); - - acpigen_write_PPC(0); - - acpigen_write_CST_package(cstate_values, cstate_count); - - acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, - CSD_HW_ALL, 0); - - generate_cppc_entries(cpu); - - acpigen_write_processor_device_end(); - } - - acpigen_write_processor_package("PPKG", 0, logical_cores); -} diff --git a/src/soc/amd/common/block/acpi/cpu_power_state.c b/src/soc/amd/common/block/acpi/cpu_power_state.c index d6b1eb3..21c032d 100644 --- a/src/soc/amd/common/block/acpi/cpu_power_state.c +++ b/src/soc/amd/common/block/acpi/cpu_power_state.c @@ -2,6 +2,7 @@
#include <acpi/acpi.h> #include <acpi/acpigen.h> +#include <amdblocks/cppc.h> #include <amdblocks/cpu.h> #include <console/console.h> #include <cpu/amd/msr.h> @@ -42,7 +43,7 @@ } }
-size_t get_cstate_info(acpi_cstate_t *cstate_values) +static size_t get_cstate_info(acpi_cstate_t *cstate_values) { size_t i; size_t cstate_count; @@ -63,3 +64,59 @@
return i; } + +void generate_cpu_entries(const struct device *device) +{ + int logical_cores; + size_t cstate_count, pstate_count, cpu; + acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} }; + struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; + struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; + uint32_t threads_per_core; + + const acpi_addr_t perf_ctrl = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 64, + .addrl = PS_CTL_REG, + }; + const acpi_addr_t perf_sts = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 64, + .addrl = PS_STS_REG, + }; + + threads_per_core = get_threads_per_core(); + cstate_count = get_cstate_info(cstate_values); + pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); + logical_cores = get_cpu_count(); + + for (cpu = 0; cpu < logical_cores; cpu++) { + acpigen_write_processor_device(cpu); + + acpigen_write_pct_package(&perf_ctrl, &perf_sts); + + acpigen_write_pss_object(pstate_values, pstate_count); + + acpigen_write_xpss_object(pstate_xpss_values, pstate_count); + + if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) + acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, + HW_ALL); + else + acpigen_write_PSD_package(0, logical_cores, SW_ALL); + + acpigen_write_PPC(0); + + acpigen_write_CST_package(cstate_values, cstate_count); + + acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, + CSD_HW_ALL, 0); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_CPPC)) + generate_cppc_entries(cpu); + + acpigen_write_processor_device_end(); + } + + acpigen_write_processor_package("PPKG", 0, logical_cores); +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index a380a2d..998ed13 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -14,7 +14,8 @@ void set_cstate_io_addr(void); void write_resume_eip(void);
-size_t get_cstate_info(acpi_cstate_t *cstate_values); +size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, + struct acpi_xpss_sw_pstate *pstate_xpss_values); const acpi_cstate_t *get_cstate_config_data(size_t *size);
#endif /* AMD_BLOCK_CPU_H */ diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 20a69b4..f1f0c53 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -249,58 +249,3 @@ *size = ARRAY_SIZE(cstate_cfg_table); return cstate_cfg_table; } - -void generate_cpu_entries(const struct device *device) -{ - int logical_cores; - size_t cstate_count, pstate_count, cpu; - acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} }; - struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; - struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; - uint32_t threads_per_core; - - const acpi_addr_t perf_ctrl = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_CTL_REG, - }; - const acpi_addr_t perf_sts = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_STS_REG, - }; - - threads_per_core = get_threads_per_core(); - cstate_count = get_cstate_info(cstate_values); - pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); - logical_cores = get_cpu_count(); - - for (cpu = 0; cpu < logical_cores; cpu++) { - acpigen_write_processor_device(cpu); - - acpigen_write_pct_package(&perf_ctrl, &perf_sts); - - acpigen_write_pss_object(pstate_values, pstate_count); - - acpigen_write_xpss_object(pstate_xpss_values, pstate_count); - - if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) - acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, - HW_ALL); - else - acpigen_write_PSD_package(0, logical_cores, SW_ALL); - - acpigen_write_PPC(0); - - acpigen_write_CST_package(cstate_values, cstate_count); - - acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, - CSD_HW_ALL, 0); - - generate_cppc_entries(cpu); - - acpigen_write_processor_device_end(); - } - - acpigen_write_processor_package("PPKG", 0, logical_cores); -} diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 1f9e253..a2990ab 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -186,8 +186,8 @@ /* * Populate structure describing enabled p-states and return count of enabled p-states. */ -static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, - struct acpi_xpss_sw_pstate *pstate_xpss_values) +size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, + struct acpi_xpss_sw_pstate *pstate_xpss_values) { msr_t pstate_def; size_t pstate_count, pstate; @@ -248,58 +248,3 @@ *size = ARRAY_SIZE(cstate_cfg_table); return cstate_cfg_table; } - -void generate_cpu_entries(const struct device *device) -{ - int logical_cores; - size_t cstate_count, pstate_count, cpu; - acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} }; - struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; - struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; - uint32_t threads_per_core; - - const acpi_addr_t perf_ctrl = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_CTL_REG, - }; - const acpi_addr_t perf_sts = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_STS_REG, - }; - - threads_per_core = get_threads_per_core(); - cstate_count = get_cstate_info(cstate_values); - pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); - logical_cores = get_cpu_count(); - - for (cpu = 0; cpu < logical_cores; cpu++) { - acpigen_write_processor_device(cpu); - - acpigen_write_pct_package(&perf_ctrl, &perf_sts); - - acpigen_write_pss_object(pstate_values, pstate_count); - - acpigen_write_xpss_object(pstate_xpss_values, pstate_count); - - if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) - acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, - HW_ALL); - else - acpigen_write_PSD_package(0, logical_cores, SW_ALL); - - acpigen_write_PPC(0); - - acpigen_write_CST_package(cstate_values, cstate_count); - - acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, - CSD_HW_ALL, 0); - - generate_cppc_entries(cpu); - - acpigen_write_processor_device_end(); - } - - acpigen_write_processor_package("PPKG", 0, logical_cores); -} diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 2646f2f..ca60e8c 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -187,8 +187,8 @@ /* * Populate structure describing enabled p-states and return count of enabled p-states. */ -static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, - struct acpi_xpss_sw_pstate *pstate_xpss_values) +size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, + struct acpi_xpss_sw_pstate *pstate_xpss_values) { msr_t pstate_def; size_t pstate_count, pstate; @@ -249,58 +249,3 @@ *size = ARRAY_SIZE(cstate_cfg_table); return cstate_cfg_table; } - -void generate_cpu_entries(const struct device *device) -{ - int logical_cores; - size_t cstate_count, pstate_count, cpu; - acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} }; - struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; - struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; - uint32_t threads_per_core; - - const acpi_addr_t perf_ctrl = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_CTL_REG, - }; - const acpi_addr_t perf_sts = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_STS_REG, - }; - - threads_per_core = get_threads_per_core(); - cstate_count = get_cstate_info(cstate_values); - pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); - logical_cores = get_cpu_count(); - - for (cpu = 0; cpu < logical_cores; cpu++) { - acpigen_write_processor_device(cpu); - - acpigen_write_pct_package(&perf_ctrl, &perf_sts); - - acpigen_write_pss_object(pstate_values, pstate_count); - - acpigen_write_xpss_object(pstate_xpss_values, pstate_count); - - if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) - acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, - HW_ALL); - else - acpigen_write_PSD_package(0, logical_cores, SW_ALL); - - acpigen_write_PPC(0); - - acpigen_write_CST_package(cstate_values, cstate_count); - - acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, - CSD_HW_ALL, 0); - - generate_cppc_entries(cpu); - - acpigen_write_processor_device_end(); - } - - acpigen_write_processor_package("PPKG", 0, logical_cores); -} diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 0bac92f..cce78cf 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -188,8 +188,8 @@ /* * Populate structure describing enabled p-states and return count of enabled p-states. */ -static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, - struct acpi_xpss_sw_pstate *pstate_xpss_values) +size_t get_pstate_info(struct acpi_sw_pstate *pstate_values, + struct acpi_xpss_sw_pstate *pstate_xpss_values) { msr_t pstate_def; size_t pstate_count, pstate; @@ -245,56 +245,3 @@ *size = ARRAY_SIZE(cstate_cfg_table); return cstate_cfg_table; } - -void generate_cpu_entries(const struct device *device) -{ - int logical_cores; - size_t cstate_count, pstate_count, cpu; - acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} }; - struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} }; - struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} }; - uint32_t threads_per_core; - - const acpi_addr_t perf_ctrl = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_CTL_REG, - }; - const acpi_addr_t perf_sts = { - .space_id = ACPI_ADDRESS_SPACE_FIXED, - .bit_width = 64, - .addrl = PS_STS_REG, - }; - - threads_per_core = get_threads_per_core(); - cstate_count = get_cstate_info(cstate_values); - pstate_count = get_pstate_info(pstate_values, pstate_xpss_values); - logical_cores = get_cpu_count(); - - for (cpu = 0; cpu < logical_cores; cpu++) { - acpigen_write_processor_device(cpu); - - acpigen_write_pct_package(&perf_ctrl, &perf_sts); - - acpigen_write_pss_object(pstate_values, pstate_count); - - acpigen_write_xpss_object(pstate_xpss_values, pstate_count); - - if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT)) - acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core, - HW_ALL); - else - acpigen_write_PSD_package(0, logical_cores, SW_ALL); - - acpigen_write_PPC(0); - - acpigen_write_CST_package(cstate_values, cstate_count); - - acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core, - CSD_HW_ALL, 0); - - acpigen_write_processor_device_end(); - } - - acpigen_write_processor_package("PPKG", 0, logical_cores); -}