[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update FSP params for Jasper Lake

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38461 )

Change subject: soc/intel/tigerlake: Update FSP params for Jasper Lake
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Patch Set 23:

(4 comments)

https://review.coreboot.org/c/coreboot/+/38461/22/src/soc/intel/tigerlake/fs... 
File src/soc/intel/tigerlake/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38461/22/src/soc/intel/tigerlake/fs... 
PS22, Line 52: 			ARRAY_SIZE(config->SerialIoI2cMode), "copy buffer overflow!");
> I think this communicates well on compilation failure.

As you want.

https://review.coreboot.org/c/coreboot/+/38461/22/src/soc/intel/tigerlake/fs... 
PS22, Line 93: respectively
*accordingly* might be more appropriate.

https://review.coreboot.org/c/coreboot/+/38461/22/src/soc/intel/tigerlake/fs... 
PS22, Line 99: 		params->PeiGraphicsPeimInit = 0;
> since too many conditions, I think if else hold good.

Done

https://review.coreboot.org/c/coreboot/+/38461/22/src/soc/intel/tigerlake/fs... 
PS22, Line 128: 	}
> can we done, but not in scope of this change. we can have a separate CL for it.

Sure.